41.8.11 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     MC3MC2MC1MC0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
 FAULT1FAULT0FAULTBFAULTADFSUFS   
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
     ERRCNTTRGOVF 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 16, 17, 18, 19 – MC Match or Capture Channel x Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which enables the Match or Capture Channel x interrupt.

ValueDescription
0 The Match or Capture Channel x interrupt is disabled.
1 The Match or Capture Channel x interrupt is enabled.

Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Non-Recoverable Fault x Interrupt Disable/Enable bit, which enables the Non-Recoverable Fault x interrupt.

ValueDescription
0 The Non-Recoverable Fault x interrupt is disabled.
1 The Non-Recoverable Fault x interrupt is enabled.

Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault x interrupt.

ValueDescription
0 The Non-Recoverable Fault x interrupt is disabled.
1 The Non-Recoverable Fault x interrupt is enabled.

Bit 13 – FAULTB Recoverable Fault B Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable Fault B interrupt.

ValueDescription
0 The Recoverable Fault B interrupt is disabled.
1 The Recoverable Fault B interrupt is enabled.

Bit 12 – FAULTA Recoverable Fault A Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recoverable Fault A interrupt.
ValueDescription
0 The Recoverable Fault A interrupt is disabled.
1 The Recoverable Fault A interrupt is enabled.

Bit 11 – DFS Non-Recoverable Debug Fault Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault State interrupt.

ValueDescription
0 The Debug Fault State interrupt is disabled.
1 The Debug Fault State interrupt is enabled.

Bit 10 – UFS Non-Recoverable Update Fault Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which disables the Non-Recoverable Update Fault interrupt.

ValueDescription
0 The Non-Recoverable Update Fault interrupt is disabled.
1 The Non-Recoverable Update Fault interrupt is enabled.

Bit 3 – ERR Error Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Error Interrupt Disable/Enable bit, which enables the Compare interrupt.

ValueDescription
0 The Error interrupt is disabled.
1 The Error interrupt is enabled.

Bit 2 – CNT Counter Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt.

ValueDescription
0 The Counter interrupt is disabled.
1 The Counter interrupt is enabled.

Bit 1 – TRG Retrigger Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt.

ValueDescription
0 The Retrigger interrupt is disabled.
1 The Retrigger interrupt is enabled.

Bit 0 – OVF Overflow Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt request.

ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.