25.6.3 Region Descriptor Structure
The ICM Region Descriptor Area is a contiguous area of system memory that the controller
and the processor can access. When the ICM controller is activated, the controller
performs a descriptor fetch operation at the DSCR address. If the Main List contains
more than one descriptor (i.e., more than one region is to be moderated), the fetch
address is DSCR + RID<<4, where RID is the region identifier.
| Offset | Structure Member | Name |
|---|---|---|
| DSCR+0x00+RID*(0x10) | ICM Region Start Address | RADDR |
| DSCR+0x04+RID*(0x10) | ICM Region Configuration | RCFG |
| DSCR+0x08+RID*(0x10) | ICM Region Control | RCTRL |
| DSCR+0x0C+RID*(0x10) | ICM Region Next Address | RNEXT |
ICM Monitoring of 3 Memory Data Blocks (Defined as 2 Regions)
The following figure shows the mandatory ICM settings to monitor three memory data blocks of the system memory (defined as two regions), with one region being not contiguous (two separate areas) and one contiguous memory area. For each said region, the SHA algorithm may be independently selected (different for each region). The wrap allows continuous monitoring.
