10.3.2 Configuration

Figure 10-1. Host-Client Relations High-Speed Bus Matrix
Table 10-1. High Speed Bus Matrix Host
High-Speed Bus Matrix Host Host ID
CM4CPU - Cortex M4 Processor 1
CM4CC - Cortex-M Cache Controller 2
DMA RD - DMA-Read 3
DMA-WR - DMA-Write 4

DSU/ICD (private test mode only) - Device Service Unit/In-Chip Debugger

 5
ICM - Integrity Check Monitor 6
ADCM - ADC Controller Module 7
Table 10-2. High-Speed Bus Matrix Client
High-Speed Bus Matrix Client Client ID
SRAM1 - SRAM Port 1 1
SRAM2 - SRAM Port 2 2
SRAM3 - SRAM Port 3 3
SRAM4 - SRAM Port 4 4
PCHE - Pre-fetch Cache of CM4CC 5
PCHE - Pre-fetch Cache of Peripherals 6
PB-B-A - Peripheral Bridge A 7
PB-B-B - Peripheral Bridge B 8
PB-B-C - Peripheral Bridge C 9
PB-PIC - Peripheral Bus PIC 10
QSPI - Quad SPI Interface 11
PUKCC - Public Key Cryptography Controller 12