6.4 I/O Ports Control Registers

Note: The following conventions are used in the following tables:
  • x = Unknown value on Reset
  • — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal
Table 6-13. PortA Register Map
Virtual Address

(0x4400_2200)

Register Bit Range Bits All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0010TRISA31:160000
15:0TRISA14TRISA13TRISA12*TRISA11*TRISA10TRISA9TRISA8TRISA7TRISA6TRISA5TRISA4TRISA3TRISA2TRISA1TRISA00000
0020PORTA31:160000
15:0RA14RA13RA12*RA11*RA10RA9RA8RA7RA6RA5RA4RA3RA2RA1RA00000
0030LATA31:160000
15:0LATA14LATA13LATA12*LATA11*LATA10LATA9LATA8LATA7LATA6LATA5LATA4LATA3LATA2LATA1LATA00000
0040ODCA31:160000
15:0ODCA14ODCA13ODCA10ODCA9ODCA8ODCA7ODCA6ODCA5ODCA4ODCA3ODCA2ODCA1ODCA00000
0050CNPUA31:160000
15:0CNPUA14CNPUA13CNPUA10CNPUA9CNPUA8CNPUA7CNPUA6CNPUA5CNPUA4CNPUA3CNPUA2CNPUA1CNPUA00000
0060CNPDA31:160000
15:0CNPDA14CNPDA13CNPDA10CNPDA9CNPDA8CNPDA7CNPDA6CNPDA5CNPDA4CNPDA3CNPDA2CNPDA1CNPDA00000
0070CNCONA31:160000
15:0ONFRZSIDLEDGEDETECT0000
0080CNENA31:160000
15:0CNENA14CNENA13CNENA10CNENA9CNENA8CNENA7CNENA6CNENA5CNENA4CNENA3CNENA2CNENA1CNENA00000
0090CNSTATA31:160000
15:0CN STATA14CN STATA13CN STATA12CN STATA11CN STATA10CN STATA9CN STATA8CN STATA7CN STATA6CN STATA5CN STATA4CN STATA3CN STATA2CN STATA1CN STATA00000
00A0CNNEA31:160000
15:0CNNEA14CNNEA13CNNEA10CNNEA9CNNEA8CNNEA7CNNEA6CNNEA5CNNEA4CNNEA3CNNEA2CNNEA1CNNEA00000
00B0CNFA31:160000
15:0CNFA14CNFA13CNFA10CNFA9CNFA9CNFA7CNFA76CNFA5CNFA4CNFA3CNFA2CNFA71CNFA00000
00C0SRCON0A31:160000
15:0SR014SR013SR010SR09SR08SR07SR06SR05SR04SR03SR01SR000000
00D0SRCON1A31:160000
15:0SR114SR113SR110SR19SR18SR17SR16SR15SR14SR13SR11SR100000
  1. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links.
Note:

* - Not applicable for PIC32CX1012BZ25048

Table 6-14. PortB Register Map
Virtual Address

(0x4400_2300)

RegisterBit RangeBitsAll Resets
31/1530/1429/1328/1227/1126/1025/924/823/722/621/520/419/318/217/116/0
0100ANSELB31:160000
15:0ANSB7ANSB6ANSB5ANSB4ANSB3ANSB2ANSB1ANSB0FFFF
0110TRISB31:160000
15:0TRISB13TRISB12TRISB11TRISB10TRISB9TRISB8TRISB7TRISB6TRISB5TRISB4TRISB3TRISB2TRISB1TRISB00000
0120PORTB31:160000
15:0RB13RB12RB11RB10RB9RB8RB7RB6RB5RB4RB3RB2RB1RB00000
0130LATB31:160000
15:0LATB13LATB12LATB11LATB10LATB9LATB8LATB7LATB6LATB5LATB4LATB3LATB2LATB1LATB00000
0140ODCB31:160000
15:0ODCB13ODCB12ODCB11ODCB10ODCB9ODCB8ODCB7ODCB6ODCB5ODCB4ODCB3ODCB2ODCB1ODCB00000
0150CNPUB31:160000
15:0CNPUB13CNPUB12CNPUB11CNPUB10CNPUB9CNPUB8CNPUB7CNPUB6CNPUB5CNPUB4CNPUB3CNPUB2CNPUB1CNPUB00000
0160CNPDB31:160000
15:0CNPDB13CNPDB12CNPDB11CNPDB10CNPDB9CNPDB8CNPDB7CNPDB6CNPDB5CNPDB4CNPDB3CNPDB2CNPDB1CNPDB00000
0170CNCONB31:160000
15:0ONFRZSIDLEDGE DETECT0000
0180CNENB31:160000
15:0CNENB13CNENB12CNENB11CNENB10CNENB9CNENB8CNENB7CNENB6CNENB5CNENB4CNENB3CNENB2CNENB1CNENB00000
0190CNSTATB31:160000
15:0CN STATB13CN STATB12CN STATB11CN STATB10CN STATB9CN STATB8CN STATB7CN STATB6CN STATB5CN STATB4CN STATB3CN STATB2CN STATB1CN STATB00000
01A0CNNEB31:160000
15:0CNNEB13CNNEB12CNNEB11CNNEB10CNNEB9CNNEB8CNNEB7CNNEB6CNNEB5CNNEB4CNNEB3CNNEB2CNNEB1CNNEB00000
01B0CNFB31:160000
15:0CNFB13CNFB12CNFB11CNFB10CNFB9CNFB8CNFB7CNFB6CNFB5CNFB4CNFB3CNFB2CNFB1CNFB00000
01C0SRCON0B31:160000
15:0SR013SR012SR011SR0100000
01D0SRCON1B31:160000
15:0SR113SR112SR111SR1100000
  1. All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links.
Note: The following conventions are used in the following tables:
  • R = Readable bit
  • W = Writable bit
  • U = Unimplemented bit, read as ‘0
  • -n = Value at POR
  • 1’ = Bit is set
  • 0’ = Bit is cleared
  • x = Bit is unknown
Table 6-15. Peripheral Pin Select Input Registers
Virtual Address

(4400_1000)

Register NameBit RangeBitsAll Resets
31/1530/1429/1328/1227/1126/1025/924/823/722/621/520/419/318/217/116/0
0000hEXTINT0R31:160000
15:0EXTINT0R[3:0]0000
0004hEXTINT1R31:160000
15:0EXTINT1R[3:0]0000
0008hEXTINT2R31:160000
15:0EXTINT2R[3:0]0000
000ChEXTINT3R31:160000
15:0EXTINT3R[3:0]0000
003ChNMIR31:160000
15:0NMIR[3:0]0000
0040hSCOM0P0R31:160000
15:0SCOM0P0R[3:0]0000
0044hSCOM0P1R31:160000
15:0SCOM0P1R[3:0]0000
0048hSCOM0P2R31:160000
15:0SCOM0P2R[3:0]0000
004ChSCOM0P3R31:160000
15:0SCOM0P3R[3:0]0000
0050hSCOM1P0R31:160000
15:0SCOM1P0R[3:0]0000
0054hSCOM1P1R31:160000
15:0SCOM1P1R[3:0]0000
0058hSCOM1P2R31:160000
15:0SCOM1P2R[3:0]0000
005ChSCOM1P3R31:160000
15:0SCOM1P3R[3:0]0000
0060hSCOM2P0R31:160000
15:0SCOM2P0R[3:0]0000
0064hSCOM2P1R31:160000
15:0SCOM2P1R[3:0]0000
0068h SCOM2P2R 31:16 0000
15:0 SCOM2P2R[3:0] 0000
006Ch SCOM2P3R 31:16 0000
15:0 SCOM2P3R[3:0] 0000
0070h SCOM3P0R 31:16 0000
15:0 SCOM3P0R[3:0] 0000
0074h SCOM3P1R 31:16 0000
15:0 SCOM3P1R[3:0] 0000
0078h SCOM3P2R 31:16 0000
15:0 SCOM3P2R[3:0] 0000
007Ch SCOM3P3R 31:16 0000
15:0 SCOM3P3R[3:0] 0000
0080h QSCKR 31:16 0000
15:0 QSCKR[3:0] 0000
0084h QD0R 31:16 0000
15:0 QD0R[3:0] 0000
0088h QD1R 31:16 0000
15:0 QD1R[3:0] 0000
008Ch QD2R 31:16 0000
15:0 QD2R[3:0] 0000
0090h QD3R 31:16 0000
15:0 QD3R[3:0] 0000
0094h REFIR 31:16 0000
15:0 REFIR[3:0] 0000
0098h CCLIN0R 31:16 0000
15:0 CCLIN0R[3:0] 0000
009Ch CCLIN1R 31:16 0000
15:0 CCLIN1R[3:0] 0000
00A0h CCLIN2R 31:16 0000
15:0 CCLIN2R[3:0] 0000
00A4h CCLIN3R 31:16 0000
15:0 CCLIN3R[3:0] 0000
00A8h CCLIN4R 31:16 0000
15:0 CCLIN4R[3:0] 0000
00ACh CCLIN5R 31:16 0000
15:0 CCLIN5R[3:0] 0000
00B0h TC0WO0G1R 31:16 0000
15:0 TC0WO0G1R[3:0] 0000
00B4h TC0WO0G2R 31:16 0000
15:0 TC0WO0G2R[3:0] 0000
00B8h TC0WO1G3R 31:16 0000
15:0 TC0WO1G3R[3:0] 0000
00BCh TC0WO1G4R 31:16 0000
15:0 TC0WO1G4R[3:0] 0000
00C0h TC1WO0G1R 31:16 0000
15:0 TC1WO0G1R[3:0] 0000
00C4h TC1WO1G2R 31:16 0000
15:0 TC1WO0G2R[3:0] 0000
00C8h TC2WO0G1R 31:16 0000
15:0 TC2WO0G1R[3:0] 0000
00CCh TC2WO0G3R 31:16 0000
15:0 TC2WO0G3R[3:0] 0000
00D0h TC2WO1G2R 31:16 0000
15:0 TC2WO1G2R[3:0] 0000
00D4h TC2WO1G4R 31:16 0000
15:0 TC2WO1G4R [3:0]
00D8h TC3WO0G1R 31:16 0000
15:0 TC3WO0G1R [3:0]
00DCh TC3WO0G3R 31:16 0000
15:0 TC3WO0G3R[3:0]
00E0h TC3WO1G2R 31:16 0000
15:0 TC3WO1G2R [3:0]
00E4h TC3WO1G4R 31:16 0000
15:0 TC3WO1G4R[3:0] 0000
Table 6-16. Peripheral Pin Select Output Registers
Virtual Address

(4400_1000) (1)

Register NameBit RangeBitsAll Resets
31/1530/1429/1328/1227/1126/1025/924/823/722/621/520/419/318/217/116/0
0200h RPA0G2R* 31:16 0000
15:0 RPA0G2R[4:0] 0000
0204h RPA0G3R* 31:16 0000
15:0 RPA0G3R[4:0] 0000
0208h RPA1G3R* 31:16 0000
15:0 RPA1G3R[4:0] 0000
020Ch RPA1G4R* 31:16 0000
15:0 RPA1G4R[4:0] 0000
0210h RPA2G1R* 31:16 0000
15:0 RPA2G1R[4:0] 0000
0214h RPA2G4R* 31:16 0000
15:0 RPA2G4R [4:0] 0000
0218h RPA3G1R 31:16 0000
15:0 RPA3G1R[4:0] 0000
021Ch RPA3G2R 31:16 0000
15:0 RPA3G2R[4:0] 0000
0220h RPA3G3R 31:16 0000
15:0 RPA3G3R[4:0] 0000
0224h RPA4G2R 31:16 0000
15:0 RPA4G2R[4:0] 0000
0228h RPA4G3R 31:16 0000
15:0 RPA4G3R[4:0] 0000
022Ch RPA4G4R 31:16 0000
15:0 RPA4G4R[4:0] 0000
0230h RPA5G1R 31:16 0000
15:0 RPA5G1R[4:0] 0000
0234h RPA5G3R 31:16 0000
15:0 RPA5G3R[4:0] 0000
0238h RPA5G4R 31:16 0000
15:0 RPA5G4R[4:0] 0000
023Ch RPA6G1R 31:16 0000
15:0 RPA6G1R[4:0] 0000
0240h RPA6G2R 31:16 0000
15:0 RPA6G2R[4:0] 0000
0244h RPA6G4R 31:16 0000
15:0 RPA6G4R[4:0] 0000
0248h RPA7G1R 31:16 0000
15:0 RPA7G1R[4:0] 0000
024Ch RPA7G2R 31:16 0000
15:0 RPA7G2R[4:0] 0000
0250h RPA8G2R 31:16 0000
15:0 RPA8G2R[4:0] 0000
0254h RPA8G3R 31:16 0000
15:0 RPA8G3R[4:0] 0000
0258h RPA8G4R 31:16 0000
15:0 RPA8G4R[4:0] 0000
025Ch RPA9G1R 31:16 0000
15:0 RPA9G1R[4:0] 0000
0260h RPA9G3R 31:16 0000
15:0 RPA9G3R[4:0] 0000
0264h RPA9G4R 31:16 0000
15:0 RPA9G4R[4:0] 0000
0268h RPA10G1R 31:16 0000
15:0 RPA10G1R[4:0] 0000
026Ch RPA10G4R 31:16 0000
15:0 RPA10G4R[4:0] 0000
0278h RPA13G3R* 31:16 0000
15:0 RPA13G3R[4:0] 0000
027Ch RPA13G4R* 31:16 0000
15:0 RPA13G4R[4:0] 0000
0280h RPA14G1R* 31:16 0000
15:0 RPA14G1R[4:0] 0000
0284h RPA14G4R* 31:16 0000
15:0 RPA14G4R[4:0] 0000
028Ch RPB0G1R* 31:16 0000
15:0 RPB0G1R[4:0] 0000
0290h RPB0G2R* 31:16 0000
15:0 RPB0G2R[4:0] 0000
0294h RPB1G2R* 31:16 0000
15:0 RPB1G2R[4:0] 0000
0298h RPB1G3R* 31:16 0000
15:0 RPB1G3R[4:0] 0000
029Ch RPB2G3R* 31:16 0000
15:0 RPB2G3R[4:0] 0000
02A0h RPB2G4R* 31:16 0000
15:0 RPB2G4R[4:0] 0000
02A4h RPB3G1R* 31:16 0000
15:0 RPB3G1R[4:0] 0000
02A8h RPB3G4R* 31:16 0000
15:0 RPB3G4R[4:0] 0000
02ACh RPB4G1R 31:16 0000
15:0 RPB4G1R[4:0] 0000
02B0h RPB4G2R 31:16 0000
15:0 RPB4G2R[4:0] 0000
02B4h RPB5G2R 31:16 0000
15:0 RPB5G2R[4:0] 0000
02B8h RPB5G3R 31:16 0000
15:0 RPB5G3R[4:0] 0000
02BCh RPB6G3R 31:16 0000
15:0 RPB6G3R[4:0] 0000
02C0h RPB6G4R 31:16 0000
15:0 RPB6G4R[4:0] 0000
02C4h RPB7G1R 31:16 0000
15:0 RPB7G1R[4:0] 0000
02C8h RPB7G4R 31:16 0000
15:0 RPB7G4R[4:0] 0000
02CCh RPB8G1R 31:16 0000
15:0 RPB8G1R[4:0] 0000
02D0h RPB8G2R 31:16 0000
15:0 RPB8G2R[4:0] 0000
02D4h RPB9G2R 31:16 0000
15:0 RPB9G2R[4:0] 0000
02D8h RPB9G3R 31:16 0000
15:0 RPB9G3R[4:0] 0000
02DCh RPB10G3R* 31:16 0000
15:0 RPB10G3R[4:0] 0000
02E0h RPB10G4R* 31:16 0000
15:0 RPB10G4R[4:0] 0000
02E4h RPB11G1R* 31:16 0000
15:0 RPB11G1R[4:0] 0000
02E8h RPB11G4R* 31:16 0000
15:0 RPB11G4R[4:0] 0000
02ECh RPB12G1R* 31:16 0000
15:0 RPB12G1R[4:0] 0000
02F0h RPB12G2R* 31:16 0000
15:0 RPB12G2R[4:0] 0000
02F4h RPB13G2R* 31:16 0000
15:0 RPB13G2R[4:0] 0000
02F8h RPB13G3R* 31:16 0000
15:0 RPB13G3R[4:0] 0000