13.17.7 Reference Oscillator x Control

Note:
  • REFOCON.ROSEL must not be written while the REFOCON.ACTIVE bit is ‘1’ – This will result in undefined behavior.
  • REFOCON must not be written when REFOCON[ON] != REFOCON[ACTIVE] – This will result in undefined behavior.
  • This register can always be accessed regardless of the cfg_sys_unlock value.
Name: REFOxCON
Offset: 0x70 + (x-1)*0x20 [x=1..6]
Reset: 0x00000000

Bit 3130292827262524 
  RODIV14RODIV13RODIV12RODIV11RODIV10RODIV9RODIV8 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
 RODIV7RODIV6RODIV5RODIV4RODIV3RODIV2RODIV1RODIV0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 ONFRZSIDLOERSLP DIVSW_ENACTIVE 
Access R/WR/WR/WR/WR/WHC/ R/WHS/HC/ R 
Reset 0000000 
Bit 76543210 
     ROSEL3ROSEL2ROSEL1ROSEL0 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 – RODIV Reference Clock Divider bits

Specifies 1/2 period of reference clock in the source clocks.

Example: Period of refo_clk = [Reference source * 2] * RODIV

ValueDescription
111111111111111REFOx clock is Base clock frequency divided by 65,534 (32,767 *2)
111111111111110REFOx clock is Base clock frequency divided by 65,532 (32,766 * 2)
...
...
...
000000000000011REFOx clock is Base clock frequency divided by 6 (3*2)
000000000000010REFOx clock is Base clock frequency divided by 4 (2*2)
000000000000001REFOx clock is Base clock frequency divided by 2 (1*2)
000000000000000REFOx clock is same frequency as Base clock (no divider)

Bit 15 – ON Output Enable bit

ValueDescription
1Reference Oscillator Module is enabled
0Reference Oscillator Module is disabled

Bit 14 – FRZ Freeze in Debug mode bit

ValueDescription
1When the emulator is in the Debug mode, module freezes operation
0When the emulator is in the Debug mode, module continues operation

Bit 13 – SIDL Peripheral Stop in Idle Mode bit

ValueDescription
1Discontinues module operation when device enters the Idle mode
0Continues module operation in the Idle mode

Bit 12 – OE Reference Clock Output Enable bit

ValueDescription
1Reference clock is driven out on REFOx pin
0Reference clock is not driven out on REFOx pin

Bit 11 – RSLP Reference Oscillator Run in Sleep bit

Note: This bit is ignored when ROSEL[3:0] = (0000 or 0001).
ValueDescription
1Reference Oscillator output continues to run in the Sleep mode
0Reference Oscillator output is disabled in the Sleep mode

Bit 9 – DIVSW_EN Clock RODIV/ROTRIM switch enabled

ValueDescription
1Clock Divider Switching is currently in progress
0Clock Divider Switch has completed

Bit 8 – ACTIVE Reference Clock Request Status bit

ValueDescription
1Reference clock request is active (User must not update this REFOCON register)
0Reference clock request is not active (User can update this REFOCON register)

Bits 0, 1, 2, 3 – ROSEL Reference Clock Source Select bits

Select one of various clock sources to be used as the reference clock.
ValueDescription
1001-1111Reserved
1000REFI pin
0111System clock (reference clock reflects any device clock switching)
0110Peripheral clock (reference clock reflects any peripheral clock switching)
0101System PLL (Clock-3)
0100LPRC
0011SOSC
0010POSC
0001System PLL (Clock-1)
0000FRC