38.5.1 Interrupt Sources
The ADC is capable of generating interrupts from the events listed in the following table.
| Interrupt Event | Description | Interrupt Enable Bit | Interrupt Status Bit |
|---|---|---|---|
| ANx Data Ready Event | Interrupt is generated upon a completion of a conversion from an analog input source (ANx). Each of the ARDYx bits is capable of generating a unique interrupt when set using the ADCBASE register. | AGIENx of ADCGIRQEN1 | ARDYx of ADCDSTAT1 register |
| Digital Comparator Event | When an conversion's comparison criteria are met by a configured and enabled digital comparator. Each of the digital comparators is capable of generating a unique interrupt when its DCMPED bit is set. | DCMPGIEN of ADCCMPCONx register | DCMPED of ADCCMPCONx register |
| Oversampling Filter Data Ready Event | When an oversampling filter has completed the accumulation/decimation process and has stored the result. | AFGIEN of ADCFLTRx register | AFRDY of ADCFLTRx register |
| Both Band Gap Voltage and ADC Reference Voltage Ready Event | Interrupt is generated when both band gap voltage and ADC reference voltage are ready. | BGVRIEN of ADCCON2 register | BGVRRDY of ADCCON2 register |
| Band Gap Fault/Reference Voltage Fault/AVDD Brown-out Fault Event | Interrupt is generated when Band Gap Fault/Reference Voltage Fault/AVDD Brown-out occurs. | REFFLTIEN of ADCCON2 register | REFFLT of ADCCON2 register |
| ADC Module Wake-up Event | Interrupt is generated when ADC wakes up after being enabled. | WKIEN0 of ADCANCON register | WKRDY0 of ADCANCON register |
| Update Ready Event | Interrupt is generated when ADC SFRs are ready to be (and can be safely) updated with new values. | UPDIEN of ADCCON3 register | UPDRDY of ADCCON3 register |