15.4 Deep Sleep Control Register

Note:
  1. All register bits are reset only in the case of a VDDBAT POR event.
Name: DSCON
Offset: 0x00
Reset: 0x00
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 DSEN XSEMAENRTCMD   RTCCWDIS 
Access R/W/HCR/WR/WR/W 
Reset 0000 
Bit 76543210 
       ZPBORDSSR 
Access R/W/C/HSR/C/HS/HC 
Reset 00 

Bit 15 – DSEN Deep Sleep Enable Bit

This bit is only writable when cfg_deep_sleep_en = 1.
ValueDescription
1 Deep Sleep mode is entered on a SLEEP/WAIT command
0 Sleep mode is entered on a SLEEP/WAIT command

Bit 13 – XSEMAEN Extended Semaphore Enable Bit

ValueDescription
1 Extended semaphores retention is enabled in Deep Sleep mode
0 Indeterminate extended semaphore retention in Deep Sleep

Bit 12 – RTCMD RTCC Module Disable Bit

ValueDescription
1 RTCC is not enabled
0 RTCC is enabled

Bit 8 – RTCCWDIS RTCC Wake-up Disable Bit

ValueDescription
1 Wake-up from RTCC is disabled
0 Wake-up from RTCC is enabled

Bit 1 – ZPBOR Zero-Power BOR Event Bit

Note:

Unlike all other events, a Zero-Power BOR event will not cause a wake-up from Deep Sleep. This bit is present only as a status bit.

ValueDescription
1 The ZPBOR was active and a BOR event was detected during Deep Sleep
0 The ZPBOR was not active or was active, but did not detect a BOR event during Deep Sleep

Bit 0 – DSSR Deep Sleep State Restored Bit

Clearing this bit will cause the xds_keepctrl_en_lv output to be negated, indicating it is safe to release all Deep Sleep configuration keeper cells. If the wake-up source was something other than an MCLR or ICD Reset, the xds_keepio_en_lv output will also be negated at the same time, indicating it is safe to release all I/O keeper cells. This bit must be cleared by software.