11.7 DEBUG Mode

In Debug mode, TAG and METADATA RAM blocks content is read/written through the AHB bus interface if the CMCC is disabled. When the CMCC is enabled, the TAG and METADATA RAM blocks are non readable.

Debug access has the same R/W properties as the CPU access for the DATA RAM block.

The TAG, METADATA and DATA RAM blocks' R/W properties are summarized in RAM Properties. See RAM Properties from the Related Links.

Use the following sequence to perform read access with the Debugger to the three RAM blocks:

• Disable the cache controller by writing a zero to the Cache Controller Enable bit in the Cache Control register (CTRL.CEN).
• Check the Cache Controller Status bit in the Cache Status register (SR.CSTS) to verify that the CMCC is successfully disabled.
• Perform a read or write access through Debugger:
  • @ CMCC_AHB_ADDR for DATA RAM,
  • @ CMCC_AHB_ADDR_TAG for TAG RAM,
  • @ CMCC_AHB_ADDR_MTDATA for METADATA RAM.
• If a write access has been performed in the TAG, METADATA, or DATA RAM in the cache section, an invalid operation must be performed before re-enabling the CMCC.