10.2.2 Interrupt Line Mapping

Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.

An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a '1' to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing '1' to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.

An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.

Depending on their criticality, the interrupt requests for one peripheral are either ORed together on system level, generating one interrupt or directly connected to an NVIC interrupt lines. This is described in the table below.

An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).

For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.


Module	Source	Line
EIC NMI – External Interrupt Control	NMI	NMI
RTCC – Real-Time Counter and Calendar	CMP A 0	0
	CMP A 1
	CMP A 2
	CMP A 3
	OVF A
	PER A 0
	PER A 1
	PER A 2
	PER A 3
	PER A 4
	PER A 5
	PER A 6
	PER A 7
	TAMPER A
EIC – External Interrupt Controller	EXTINT 0	1
	EXTINT 1
	EXTINT 2
	EXTINT 3
FREQM – Frequency Meter	DONE	2
Flash Subsystem	Flash Controller	3
	PFW
	PCACHE
PORT-A	PortA Input Change Interrupt	4
PORT-B	PortB Input Change Interrupt	5
DMAC – Direct Memory Access Controller	SUSP 0..3	6
	TCMPL 0..3
	TERR 0..3
	SUSP 4..15	7
	TCMPL 4..15
	TERR 4..15
EVSYS – Event System Interface	EVD 0..3	8
	OVR 0..3	8
	EVD 4..11	9
	OVR 4..11	9
PAC – Peripheral Access Controller	ERR	10
RAM ECC	SINGLEE-0	11
RAM ECC	DualE-1	11
SERCOM0 – Serial Communication Interface 0⁽¹⁾ Order: USART, I2CM, I2CS, SPI	0	12
	1
	2
	3
	4
	5
	7
SERCOM1 – Serial Communication Interface 1⁽¹⁾ Order: USART, I2CM, I2CS, SPI	0	13
	1
	2
	3
	4
	5
	7
SERCOM2 – Serial Communication Interface 2⁽¹⁾ Order: USART, I2CM, I2CS, SPI	0	14
	1
	2
	3
	4
	5
	7
SERCOM3 – Serial Communication Interface 3⁽¹⁾ Order: USART, I2CM, I2CS, SPI	0	15
	1
	2
	3
	4
	5
	7
TCC0 – Timer Counter Control 0	CNT A	16
	DFS A
	ERR A
	FAULTA A
	FAULTB A
	FAULT0 A
	FAULT1 A
	OVF
	TRG
	UFS A
	MC 0
	MC 1
	MC 2
	MC 3
	MC 4
	MC 5
TCC1 – Timer Counter Control 1	CNT A	17
	DFS A
	ERR A
	FAULTA A
	FAULTB A
	FAULT0 A
	FAULT1 A
	OVF
	TRG
	UFS A
	MC 0
	MC 1
	MC 2
	MC 3
	MC 4
	MC 5
TCC2 – Timer Counter Control 2	CNT A	18
	DFS A
	ERR A
	FAULTA A
	FAULTB A
	FAULT0 A
	FAULT1 A
	OVF
	TRG
	UFS A
	MC 0
	MC 1
TC0 – Basic Timer Counter 0	ERR A	19
	MC 0
	MC 1
	OVF
TC1 – Basic Timer Counter 1	ERR A	20
	MC 0
	MC 1
	OVF
TC2 – Basic Timer Counter 2	ERR A	21
	MC 0
	MC 1
	OVF
TC3 – Basic Timer Counter 3	ERR A	22
	MC 0
	MC 1
	OVF
ADCTRL	ADC_GIRQ	23
	ADC_DIRQ0, ADC_DIRQ1
	ADC_AIRQ0, ADC_AIRQ1
	ADC_FLT	34
	ADC_EOS	35
	ADC_BGVR_RDY	36
AC – Analog Comparators	COMP 0	24
	COMP 1
	WIN 0
AES – Advanced Encryption Standard	ENCCMP	25
AES – Advanced Encryption Standard	GFMCMP	25
TRNG – True Random Generator	IS0	26
ICM – Integrity Check Monitor	ICM	27
QSPI – Quad SPI interface	QSPI	29
Wireless Radio	ZB_INT0	30
	BT_INT0	31
	BT_INT1	32
	ARBITER	33
	CLKI_WAKEUP_NMI	37
	BT_LC	38
	BT_RC	39

Note:

The integer number specified in the source refers to the respective bit position in the INTFLAG register of the respective peripheral.