The SAM L22 Xplained Pro headers EXT1, EXT2, and
EXT3 offer access to the I/O of the microcontroller in order to expand the board, e.g.
by connecting extensions to the board. These headers are based on the standard extension
header specified in the table below. The headers have a pitch of 2.54mm.
Table 4-1. Extension Header EXT1| EXT1 pin | SAM L22 pin | Function | Shared functionality |
|---|
| 1 [ID] | - | - | Communication line to the ID chip on an extension
board |
| 2 [GND] | - | - | Ground |
| 3 [ADC(+)] | PA02 | AIN[0] | - |
| 4 [ADC(-)] | PA03 | AIN[1] | Shield |
| 5 [GPIO1] | PA20 | GPIO (RTS) | - |
| 6 [GPIO2] | PA21 | GPIO (CTS) | - |
| 7 [PWM(+)] | PB08 | TC0/WO[0] | - |
| 8 [PWM(-)] | PB09 | TC0/WO[1] | - |
| 9 [IRQ/GPIO] | PC02 | IRQ10/GPIO | - |
| 10 [SPI_SS_B/GPIO] | PC03 | GPIO | - |
| 11 [TWI_SDA] | PB30 | SERCOM5 PAD[0] I²C SDA | EXT2, EXT3, Shield, Crypto, and EDBG I²C |
| 12 [TWI_SCL] | PB31 | SERCOM5 PAD[1] I²C SCL | EXT2, EXT3, Shield, Crypto, and EDBG I²C |
| 13 [USART_RX] | PA23 | SERCOM2 PAD[1] UART RX | - |
| 14 [USART_TX] | PA22 | SERCOM2 PAD[0] UART TX | - |
| 15 [SPI_SS_A] | PB21 | SERCOM3 PAD[1] SPI SS | - |
| 16 [SPI_MOSI] | PB00 | SERCOM3 PAD[2] SPI MOSI | - |
| 17 [SPI_MISO] | PB02 | SERCOM3 PAD[0] SPI MISO | - |
| 18 [SPI_SCK] | PB01 | SERCOM3 PAD[3] SPI SCK | - |
| 19 [GND] | - | - | Ground |
| 20 [VCC] | - | - | Power for extension board |
Table 4-2. Extension Header EXT2| EXT2 pin | SAM L22 pin | Function | Shared functionality |
|---|
| 1 [ID] | - | - | Communication line to the ID chip on an extension
board |
| 2 [GND] | - | - | Ground |
| 3 [ADC(+)] | PA04 | AIN[4] | Shield |
| 4 [ADC(-)] | PA05 | AIN[5] | Shield |
| 5 [GPIO1] | PB04 | GPIO | EDBG GPIO0, SLCD, and XAM |
| 6 [GPIO2] | PB05 | GPIO | EDBG GPIO1, SLCD, and XAM |
| 7 [PWM(+)] | PC28 | TCC0/WO[4] | SLCD |
| 8 [PWM(-)] | PA27 | TCC0/WO[5] | SLCD |
| 9 [IRQ/GPIO] | PC00 | IRQ8/GPIO | Shield and EDBG GPIO2 |
| 10 [SPI_SS_B/GPIO] | PC01 | GPIO | Shield, User SW0, and EDBG GPIO3 |
| 11 [TWI_SDA] | PB30 | SERCOM5 PAD[0] I²C SDA | EXT1, EXT3, Shield, Crypto, and EDBG I²C |
| 12 [TWI_SCL] | PB31 | SERCOM5 PAD[1] I²C SCL | EXT1, EXT3, Shield, Crypto, and EDBG I²C |
| 13 [USART_RX] | PA13 | SERCOM3 PAD[1] UART RX | - |
| 14 [USART_TX] | PA12 | SERCOM3 PAD[0] UART TX | - |
| 15 [SPI_SS_A] | PA17 | SERCOM1 PAD[1] SPI SS | - |
| 16 [SPI_MOSI] | PA18 | SERCOM1 PAD[2] SPI MOSI | - |
| 17 [SPI_MISO] | PA16 | SERCOM1 PAD[0] SPI MISO | - |
| 18 [SPI_SCK] | PA19 | SERCOM1 PAD[3] SPI SCK | - |
| 19 [GND] | - | - | Ground |
| 20 [VCC] | - | - | Power for extension board |
Table 4-3. Extension Header EXT3| EXT3 pin | SAM L22 pin | Function | Shared functionality |
|---|
| 1 [ID] | - | - | Communication line to the ID chip on an extension
board |
| 2 [GND] | - | - | Ground |
| 3 [ADC(+)] | PA06 | AIN[8] | SLCD |
| 4 [ADC(-)] | PA07 | AIN[9] | SLCD |
| 5 [GPIO1] | PC16 | GPIO | SLCD |
| 6 [GPIO2] | PC17 | GPIO | SLCD |
| 7 [PWM(+)] | PB16 | TC2/WO[0] | SLCD |
| 8 [PWM(-)] | PB17 | TC2/WO[1] | SLCD |
| 9 [IRQ/GPIO] | PB18 | IRQ2/GPIO | SLCD |
| 10 [SPI_SS_B/GPIO] | PB19 | GPIO | SLCD |
| 11 [TWI_SDA] | PB30 | SERCOM5 PAD[0] I²C SDA | EXT1, EXT2, Shield, Crypto, and EDBG I²C |
| 12 [TWI_SCL] | PB31 | SERCOM5 PAD[1] I²C SCL | EXT1, EXT2, Shield, Crypto, and EDBG I²C |
| 13 [USART_RX] | PA15 | SERCOM4 PAD[3] UART RX | SLCD |
| 14 [USART_TX] | PA14 | SERCOM4 PAD[2] UART TX | SLCD |
| 15 [SPI_SS_A] | PA09 | SERCOM0 PAD[1] SPI SS | SLCD |
| 16 [SPI_MOSI] | PA10 | SERCOM0 PAD[2] SPI MOSI | SLCD |
| 17 [SPI_MISO] | PA08 | SERCOM0 PAD[0] SPI MISO | SLCD |
| 18 [SPI_SCK] | PA11 | SERCOM0 PAD[3] SPI SCK | SLCD |
| 19 [GND] | - | - | Ground |
| 20 [VCC] | - | - | Power for extension board |
