1.2 Pin Descriptions

Table 1-1. SY75712 Pin Descriptions
Pin #	Pin Name	Type	Functional Description
Input Reference
1	IN	I	LVCMOS Input Reference. Input frequency range >0 Hz to 250 MHz. Input has a fail-safe circuit to prevent oscillation if the input is not driven. >0 Hz because OE is synchronous and requires three to five clock cycles to enable/disable the output. The device can transfer a DC level, but it needs three to five cycles for output to be enabled/disabled. This pin is pulled down internally with 100 kΩ to 300 kΩ resistor.
Output Clocks
3 8	OUT0 OUT1	O	Ultra-Low Additive Jitter LVCMOS Outputs. Output frequency range >0 Hz to 250 MHz. These outputs have an embedded series resistance of 50Ω (at 1.2V VDD) >0 Hz because OE is synchronous and requires three to five clock cycles to enable/disable the output. The device can transfer a DC level, but it needs three to five cycles for output to be enabled/disabled.
Control Input
2	OE	I	Output Enable (Synchronous). When low, the outputs are low; when high, the outputs are enabled. This pin is pulled down internally with 100 kΩ to 300 kΩ resistors.
Power and Ground
6	VDD	P	Positive Supply Voltage. Connect to supply of 1.2V to 1.8V.
4	GND	P	Ground. Connect to ground.
No Connect
5, 7	NC	N/A	No connect. Leave open or connect to ground.

Table 1-2. SY75714 Pin Descriptions
Pin #	Pin Name	Type	Functional Description
Input Reference
1	IN	I	LVCMOS Input Reference. Input frequency range >0 Hz to 250 MHz. Input has a fail-safe circuit to prevent oscillation if the input is not driven. >0 Hz because OE is synchronous and requires three to five clock cycles to enable/disable the output. The device can transfer a DC level, but it needs three to five cycles for output to be enabled/disabled. This pin is pulled down internally with 100 kΩ to 300 kΩ resistor.
Output Clocks
3 8 5 7	OUT0 OUT1 OUT2 OUT3	O	Ultra-Low Additive Jitter LVCMOS Outputs. Output frequency range >0 Hz to 250 MHz. These outputs have an embedded series resistance of 50Ω (at 1.2V VDD). >0 Hz because OE is synchronous and requires three to five clock cycles to enable/disable the output. The device can transfer a DC level, but it needs three to five cycles for output to be enabled/disabled.
Control Input
2	OE	I	Output Enable (Synchronous). When low, the outputs are low; when high, the outputs are enabled. This pin is pulled down internally with 100 kΩ to 300 kΩ resistors.
Power and Ground
6	VDD	P	Positive Supply Voltage. Connect to supply of 1.2V to 1.8V.
4	GND	P	Ground. Connect to ground.