15 Interrupts

Interrupt processing is an important aspect of most microcontroller applications. Interrupts may be used to synchronize software operations with events that occur in real time. When interrupts occur, the normal flow of software execution is suspended and special functions are invoked to process the event. At the completion of interrupt processing, previous context information is restored and normal execution resumes.

This chapter presents an overview of interrupt processing. The following items are discussed:

  • 15.1 Interrupt Operation – An overview of how interrupts operate.
  • 15.2 Writing an Interrupt Service Routine – You can designate one or more C functions as Interrupt Service Routines (ISRs) to be invoked by the occurrence of an interrupt. For best performance in general, place lengthy calculations or operations that require library calls in the main application. This strategy optimizes performance and minimizes the possibility of losing information when interrupt events occur rapidly.
  • 15.3 Specifying the Interrupt Vector – The DSC devices use interrupt vectors to transfer application control when an interrupt occurs. An interrupt vector is a dedicated location in program memory that specifies the address of an ISR. Applications must contain valid function addresses in these locations to use interrupts.
  • 15.4 Interrupt Service Routine Context Saving – To handle returning from an interrupt to code in the same conditional state as before the interrupt, context information from specific registers must be saved.
  • 15.5 Nesting Interrupts – The time between when an interrupt is called and when the first ISR instruction is executed is the latency of the interrupt.
  • 15.6 Enabling/Disabling Interrupts - dsPIC33C/E/F and dsPIC30 Devices Only [DD] – How interrupt priorities are determined. Enabling and disabling interrupt sources occurs at two levels: globally and individually.
  • 15.7 ISR Considerations– Sharing memory with mainline code, PSV usage with ISRs, and calling functions within ISRs.