25.3.2.1 Master Mode Operation

In master mode, the SPI interface has no automatic control of the SS line. If the SS pin is used, it must be configured as output and controlled by user software. If the bus consists of several SPI slaves and/or masters, a SPI master can use general purpose I/O pins to control the SS line to each of the slaves on the bus.

Writing a byte to the DATA register starts the SPI clock generator and the hardware shifts the eight bits into the selected slave. After shifting one byte and when there is no pending data, the Data Register Empty Interrupt flag (DREIF) in SPI.INTFLAGS is set, the SPI clock generator stops, and the Transfer Complete interrupt flag (TXCIF) in SPI.INTFLAGS is set.

If there is pending data, the flag DREIF is cleared; the master will continue to shift out the next bytes. After each byte is shifted out, the new data is copied to the shift register and the DREIF flag is set. Only when a shift is completed and there is no more pending data, the TXCIF flag is set. An end-of-transfer can also be signaled by pulling the SS line high. The last incoming byte will be kept in the shift register.

If the SS pin is not used it can be disabled by writing the Slave Select Disable bit (SSD) in the Control B register (SPI.CTRLB). If not disabled and configured as input, the pin must be held high to ensure master operation.

If the SS pin is set as input and is being driven low, the SPI peripheral will interpret this as another master trying to take control of the bus. To avoid bus contention, the master will take the following action: