34.5.4 Control B

Writing a ‘1’ to this bit disables the NACK signature sent by the UPDI when a System Reset is issued during ongoing LD(S) and ST(S) operations.

Writing a ‘1’ to this bit disables contention detection. Writing a ‘0’ to this bit enables contention detection.

Writing a ‘1’ to this bit disables the UPDI PHY interface. The clock request from the UPDI is lowered, and the UPDI is reset. All the UPDI PHY configurations and keys will be reset when the UPDI is disabled.