12.5.2 Main Clock Control B

Note:
  1. If the PBDIV bit is set, only prescaler settings matching 2n will be available, and the division will change as if PDIV[3] = 0.
Name: MCLKCTRLB
Offset: 0x01
Reset: 0x11
Property: Configuration Change Protection

Bit 76543210 
   PBDIVPDIV[3:0]PEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 010001 

Bit 5 – PBDIV  Prescaler B Division

If this bit is ‘1’, the clock frequencies for the CLK_PER and CLK_CPU will be set relative to the CLK_PER4 clock. When the Prescaler B Division (PBDIV) bit and Prescaler Enable (PEN) bit are ‘1’, only prescaler settings matching 2n are available for PDIV.

ValueNameDescription
0x0 NONE No Division
0x1 DIV4 Divide by 4

Bits 4:1 – PDIV[3:0]  Prescaler Division

This bit field defines the division ratio of the Main Clock (CLK_MAIN) prescaler A when the Prescaler Enable (PEN) bit is ‘1’. This bit field can be written at run-time to control the frequency of the CLK_PER4 clock relative to the Main Clock (CLK_MAIN).

Note: Configuration of the input frequency (CLK_MAIN) and prescaler settings must not exceed the allowed maximum frequency of the peripheral clock (CLK_PER) or CPU clock (CLK_CPU). Refer to the Electrical Characteristics section for further information.
Value Name Description Value if PBDIV = 1 (1)
0x0 DIV2 Divide by 2 DIV2
0x1 DIV4 Divide by 4 DIV4
0x2 DIV8 Divide by 8 DIV8
0x3 DIV16 Divide by 16 DIV16
0x4 DIV32 Divide by 32 DIV32
0x5 DIV64 Divide by 64 DIV64
0x6-0x7 - Reserved -
0x8 DIV6 Divide by 6 DIV2
0x9 DIV10 Divide by 10 DIV4
0xA DIV12 Divide by 12 DIV8
0xB DIV24 Divide by 24 DIV16
0xC DIV48 Divide by 48 DIV32
0xD-0xF - Reserved -

Bit 0 – PEN Prescaler Enable

This bit controls whether the Main Clock (CLK_MAIN) prescaler is enabled.

ValueDescription
0 The CLK_MAIN prescaler is disabled
1 The CLK_MAIN prescaler is enabled, and the division ratio is controlled by the Prescaler Division (PDIV) bit field
If the PBDIV bit is set, only prescaler settings matching 2n will be available, and the division will change as if PDIV[3] = 0.