12.5.2 Main Clock Control B

Note:
  1. If the PBDIV bit is set, only prescaler settings matching 2n will be available, and the division will change as if PDIV[3] = 0.
Name: MCLKCTRLB
Offset: 0x01
Reset: 0x11
Property: Configuration Change Protection

Bit 76543210 
   PBDIVPDIV[3:0]PEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 010001 

Bit 5 – PBDIV  Prescaler B Division

If this bit is ‘1’, the clock frequencies for the CLK_PER and CLK_CPU will be set relative to the CLK_PER4 clock. When the Prescaler B Division (PBDIV) bit and Prescaler Enable (PEN) bit are ‘1’, only prescaler settings matching 2n are available for PDIV.

ValueNameDescription
0x0NONENo Division
0x1DIV4Divide by 4

Bits 4:1 – PDIV[3:0]  Prescaler Division

This bit field defines the division ratio of the Main Clock (CLK_MAIN) prescaler A when the Prescaler Enable (PEN) bit is ‘1’. This bit field can be written at run-time to control the frequency of the CLK_PER4 clock relative to the Main Clock (CLK_MAIN).

Note: Configuration of the input frequency (CLK_MAIN) and prescaler settings must not exceed the allowed maximum frequency of the peripheral clock (CLK_PER) or CPU clock (CLK_CPU). Refer to the Electrical Characteristics section for further information.
ValueNameDescriptionValue if PBDIV = 1 (1)
0x0DIV2Divide by 2DIV2
0x1DIV4Divide by 4DIV4
0x2DIV8Divide by 8DIV8
0x3DIV16Divide by 16DIV16
0x4DIV32Divide by 32DIV32
0x5DIV64Divide by 64DIV64
0x6-0x7-Reserved-
0x8DIV6Divide by 6DIV2
0x9DIV10Divide by 10DIV4
0xADIV12Divide by 12DIV8
0xBDIV24Divide by 24DIV16
0xCDIV48Divide by 48DIV32
0xD-0xF-Reserved-

Bit 0 – PEN Prescaler Enable

This bit controls whether the Main Clock (CLK_MAIN) prescaler is enabled.

ValueDescription
0The CLK_MAIN prescaler is disabled
1The CLK_MAIN prescaler is enabled, and the division ratio is controlled by the Prescaler Division (PDIV) bit field
If the PBDIV bit is set, only prescaler settings matching 2n will be available, and the division will change as if PDIV[3] = 0.