12.5.9 PLL Control A

Bit 7 – RUNSTDBY Run Standby

This bit controls whether the Phase-Locked Loop (PLL) is always running.

Note:

The requesting peripheral must take the PLL start-up time and PLL source start-up time into account.
The oscillator signal will only be available if requested and will be available after two PLL cycles.

Value	Description
0	The PLL will only run if requested by a peripheral ⁽¹⁾
1	The PLL will always run in Active, Idle and Standby sleep modes ⁽²⁾

This bit controls the Phase-Locked Loop (PLL) clock source.


Value	Name	Description
`0x0`	OSCHF	Internal high-frequency oscillator as PLL source
`0x1`	EXTCLK	External clock as PLL source
`0x2-0x3`	Reserved

This bit field divides the source frequency before being used as input to the PLL.


Value	Name	Description
`0x0`	NONE	No division. Nominal source frequency 2.5 to 5.5 MHz
`0x1`	DIV2	Divide by 2. Nominal source frequency 5 to 11 MHz
`0x2`	DIV4	Divide by 4. Nominal source frequency 10 to 22 MHz
`0x3`	DIV6	Divide by 6. Nominal source frequency 15 to 33 MHz

This bit field controls the multiplication factor for the Phased-Locked Loop (PLL).

Name:	PLLCTRLA
Offset:	0x10
Reset:	0x00
Property:	Configuration Change Protection