2 Cache Memory vs TCM Overview

This chapter highlights the key differences between Cache memory and TCM.

Table 2-1. TCM vs Cache
Tightly Coupled Memory	Cache Memory
Tightly Coupled Memory is accessed by a dedicated connection from the core. In the PIC32CZ CA and SAM E70/S70/V7x family of microcontrollers, there are two dedicated connections from the Cortex-M7 core to the internal SRAM for Instruction TCM and another for Data TCM.	Cache memory is RAM integrated inside the Cortex-M7 core itself. In the PIC32CZ CA and SAM E70/S70/V7x series of microcontrollers, 16 KB of instruction cache (I-cache) and 16 KB of data cache (D-cache) are available.
Tightly coupled memory is part of the system memory map with a definite start address. The size of the TCM determines the end address	Cache memory is not part of the system memory map. It does not have a physical memory address.
A programmer can decide where the content will be stored in TCM at compilation time.	A control logic, not the programmer, determines what is stored in cache memory.
TCM is directly accessible to software.	During program execution, the cache is stored with instructions or data fetched from memory to the CPU.
TCM can be accessed by CPU and DMA.	Cache cannot be accessed by DMA.
TCM has deterministic access time. It always takes a single cycle to access contents from TCM.	Cache memory serves as an intermediate buffer between the processor and memory to reduce memory access time. The number of cycles needed to access a memory location differs for a cache hit and a cache miss.

Note: TCM contents are not cached. TCM is directly connected to the Cortex-M7 core by a bus. It can be accessed at similar speeds as accessing the cache without penalty for a cache miss and coherence issues.