8 Observing the Output on the MPLAB Data Visualizer
- After building and programming the
application, open MPLAB Data Visualizer by clicking the highlighted icon.
Figure 8-1. Launching MPLAB Data Visualizer - To configure the Serial Port of the
PIC32CZ CA90 Curiosity Ultra Evaluation Board, click on the Gear icon as
shown below:
Figure 8-2. Serial Port Setup - On the COM Settings propery
sheet, for Baud Rate, enter 115200.
Figure 8-3. Selecting Baud Rate - Open the Serial Port of the PIC32CZ
CA90 Curiosity Ultra Evaluation Board by clicking the Play icon.
Figure 8-4. Opening the Serial Port - Select Send to Terminal to
visualize the TCM performance test results, and then click Close.
Figure 8-5. Select the Terminal Option - Press the Reset button on the
Evaluation Board to reset the device.
Figure 8-6. Resetting the PIC32CZ CA90 Curiosity Ultra Evaluation Board Figure 8-7. Resetting the SAM E70 Xplained Ultra Evaluation Kit - Observe the console message TCM
Performance Demo displayed on the MPLAB Data Visualizer.
Figure 8-8. TCM Performance Comparison Note:- The optimization level is set to None / O0 for both projects.
- Execution metrics collected for the PIC32CZ CA and SAM E70/S70/V70/V71 family of devices are provided in the following tables:
- The following tables provide the
benefits of ITCM and DTCM compared to traditional Flash/SRAM combinations. It is
noted that the advantage is minimal when cache is enabled, as the example program is
very small and fits entirely within the cache. However, real-world applications are
significantly more complex and cannot be fully contained within the cache. For such
applications, TCM proves to be more advantageous in managing critical and
deterministic code segments.
Table 8-1. PIC32CZ CA: TCM Configuration - 128 KB, Optimization – None / O0 Configuration Code Buffer Cycles Instruction Cache = OFF; Data Cache = OFF;
Flash SRAM 1085171 Flash DTCM 988133 SRAM SRAM 955135 SRAM DTCM 876161 ITCM SRAM 916673 ITCM DTCM 834131 Instruction Cache = ON; Data Cache = OFF;
Flash SRAM 1035921 Flash DTCM 938207 SRAM SRAM 944315 SRAM DTCM 853327 ITCM SRAM 898183 ITCM DTCM 834117 Instruction Cache = ON; Data Cache = ON;
Flash SRAM 166569 Flash DTCM 163984 SRAM SRAM 163995 SRAM DTCM 163982 ITCM SRAM 163981 ITCM DTCM 163981 Table 8-2. SAM E70/S70/V70/V71: TCM Configuration - 32 KB, Optimization – None / O0 Configuration Code Buffer Cycles Instruction Cache = OFF; Data Cache = OFF;
Flash SRAM 1317577 Flash DTCM 1258257 SRAM SRAM 1186391 SRAM DTCM 1064289 ITCM SRAM 1039041 ITCM DTCM 964571 Instruction Cache = ON; Data Cache = OFF;
Flash SRAM 1266171 Flash DTCM 1161249 SRAM SRAM 1169437 SRAM DTCM 1051603 ITCM SRAM 1052657 ITCM DTCM 963431 Instruction Cache = ON; Data Cache = ON;
Flash SRAM 167639 Flash DTCM 163973 SRAM SRAM 164019 SRAM DTCM 164034 ITCM SRAM 163971 ITCM DTCM 163973 - To enhance these figures, adjust the
optimization level to O2 to observe the improvements:
- In the MPLAB X IDE Project Properties window, under Categories, click and expand Conf: [pic32cz_ca90_cult] > XC32 (Global Options), and then select xc32-gcc.
- In the right Options for
xc32-gcc properties sheet:
- For Option categories, select Optimization.
- For Optimization level, select 2.
Figure 8-9. Project Properties - Click Apply, and then click OK.
- To rebuild and program the PIC32CZ
CA90 Curiosity Ultra Evaluation Board, refer to the Building and Programming the
Application.Note:
- Execution metrics collected for the PIC32CZ CA and SAM E70/S70/V70/V71 family are provided in the following tables:
- These above steps can be used to change the optimization level for the SAM E70 Xplained Ultra Evaluation Kit.
Table 8-3. PIC32CZ CA: TCM Configuration - 128 KB, Optimization – O2 Configuration Code Buffer Cycles Instruction Cache = OFF; Data Cache = OFF;
Flash SRAM 383503 Flash DTCM 385553 SRAM SRAM 179778 SRAM DTCM 134154 ITCM SRAM 181595 ITCM DTCM 133951 Instruction Cache = ON; Data Cache = OFF;
Flash SRAM 179485 Flash DTCM 136405 SRAM SRAM 179496 SRAM DTCM 133842 ITCM SRAM 181515 ITCM DTCM 133851 Instruction Cache = ON; Data Cache = ON;
Flash SRAM 45442 Flash DTCM 45203 SRAM SRAM 39094 SRAM DTCM 42650 ITCM SRAM 41132 ITCM DTCM 42640 Table 8-4. SAM E70/S70/V70/V71: TCM Configuration - 32 KB, Optimization – O2 Configuration Code Buffer Cycles Instruction Cache = OFF; Data Cache = OFF;
Flash SRAM 394969 Flash DTCM 397011 SRAM SRAM 215731 SRAM DTCM 159931 ITCM SRAM 215575 ITCM DTCM 159709 Instruction Cache = ON; Data Cache = OFF;
Flash SRAM 214951 Flash DTCM 163591 SRAM SRAM 216901 SRAM DTCM 161029 ITCM SRAM 216859 ITCM DTCM 161013 Instruction Cache = ON; Data Cache = ON;
Flash SRAM 47036 Flash DTCM 45180 SRAM SRAM 41120 SRAM DTCM 42636 ITCM SRAM 41101 ITCM DTCM 42633 The following graphs represent the TCM performance on the PIC32CZ CA and SAM E70/S70/V70/V71 Family of devices.
Figure 8-10. PIC32CZ CA: Disabled Instruction Cache and Data Cache Figure 8-11. PIC32CZ CA: Enabled Instruction Cache Figure 8-12. PIC32CZ CA: Enabled Instruction Cache and Data Cache Figure 8-13. SAM E70/S70/V70/V71: Disabled Instruction Cache and Data Cache Figure 8-14. SAM E70/S70/V70/V71: Enabled Instruction Cache Figure 8-15. SAM E70/S70/V70/V71: Enabled Instruction Cache and Data Cache