1.3.2 Defining State Machines

A state machine is a digital device that traverses a predetermined sequence of states in an orderly fashion. A synchronous state machine is a logic circuit with flip-flops. Because its output can be fed back to its own or to another flip-flop’s input, a flip-flop’s input value may depend on both its own output and the output of other flip-flops; consequently, its final output value depends on its own previous values, as well as those of other flip-flops.

The CUPL state-machine model, as shown in Figure 2-3, uses six components: inputs, combinatorial logic, storage registers, state bits, registered outputs and non-registered outputs.

Figure 1-3. State Machine Model

Inputs - are signals entering the device that originate from some other device.

Combinatorial Logic is any combination of logic gates (usually AND-OR) that produces an output signal that is valid Tpd (propagation delay time) nanoseconds after any of the signals driving these gates change. Tpd is the delay between the initiation of an input or feedback event and the occurrence of a non-registered output.

State Bits are storage register outputs that are fed back to drive the combinatorial logic. They contain the present-state information.

Storage Registers are any flip-flop elements that receive their inputs from the state machine’s combinatorial logic. Some registers are used for state bits, while others are used for registered outputs. The registered output is valid Tco (clock to out time) nanoseconds after the clock pulse occurs. Tco is the time delay between the initiation of a clock signal and the occurrence of a valid flip-flop output.

To implement a state machine, CUPL supplies a syntax that allows the description of any function in the state machine. The SEQUENCE keyword identifies the outputs of a state machine and is followed by statements that define the function of the state machine. The SEQUENCE keyword causes the storage registers and registered output types generated to be the default type for the target device. Along with the SEQUENCE keyword are the SEQUENCED, SEQUENCEJK, SEQUENCERS and SEQUENCET keywords. Respectively, they force the state registers and registered outputs to be generated as D, J-K, S-R, and T-type flip-flops. The format for the SEQUENCE syntax is as follows:


`SEQUENCE state_var_list {`
	`PRESENT state_n0`
		`IF(condition1)NEXT state_n1;`
		`IF (condition2) NEXT state_n2 OUT out_n0;`
		`DEFAULT NEXT state_n0;`
	`PRESENT state_n1`
		`NEXT state_n2;`
	.
	.
	.
	`PRESENT state_nn statements;`
`}`

where

state_var_list is a list of the state bit variables used in the state machine block. The variable list can be represented by a field variable.

state_n is the state number and is a decode value of the state_variable_list and must be unique for each present statement.

statements are any of the conditional, next, or output statements described in the following subsection.