2.3 Pin Functions of the dsPIC DSC
The on-board dsPIC33CDVC256MP506 device controls various features of the Reference Design through its peripherals and CPU capability. Pin functions of the dsPIC® DSC are grouped according to their functionality and presented below.
| Signal | dsPIC DSC Pin No. | dsPIC DSC Pin Function | dsPIC DSC Peripheral | Remarks |
|---|---|---|---|---|
| dsPIC DSC Configuration - Supply, Clock, Reset and Programming | ||||
| +3.3V | 25, 41, 52 | VDD | Supply | +3.3V Digital supply to dsPIC DSC |
| GND | 26, 40, 65 | VSS | Ground | |
| +3.3V | 19 | AVDD | +3.3V Analog supply to dsPIC DSC | |
| GND | 20 | AVSS | GND | |
| MCLR | 12 | MCLR | Reset | Connects to ICSP Header (J6) |
| PGD | 42 | PGD3/RP37/SDA2/PMA14/PMCS1/PSCS/RB5 | In-Circuit Serial Programming (ICSP™) or In-Circuit debugger | |
| PGC | 44 | PGC3/RP38/SCL2/RB6 | ||
| dsPIC DSC Internal Amplifier Connections for Current Amplification | ||||
| OA1IN+ | 16 | OA1IN+/AN9/PMA6/RA2 | Operational Amplifier 1 (Op Amp 1) and Shared ADC Core | Differential current feedback from shunt resistor Rsh3 connects to non-inverting and inverting inputs of Op Amp 1 through input resistors. |
| OA1IN- | 15 | OA1IN-/ANA1/RA1 | ||
| IBUS | 14 | OA1OUT/AN0/CMP1A/IBIAS0/RA0 | Op Amp 1 Output, which is an amplified bus current. For the output to be available, configure and enable Op Amp 1. | |
| OA2IN+ | 35 | PGC2/OA2IN+/RP36/RB4 | Operational Amplifier 2 (Op Amp 2) and Shared ADC Core | Differential current feedback from shunt resistor Rsh1 connects to non-inverting and inverting inputs of Op Amp 2 through input resistors. |
| OA2IN- | 34 | PGD2/OA2IN-/AN8/RP35/RB3 | ||
| IA | 33 | OA2OUT/AN1/AN7/ANA0/CMP1D/CMP2D/CMP3D/RP34/SCL3/INT0/RB2 | Op Amp 2 Output, which is an amplified phase A current. For the output to be available, configure and enable Op Amp 2. | |
| OA3IN+ | 23 | OA3IN+/AN14/CMP2B/ISRC1/RP50/PMD13/ PMA13/RC2 | Operational Amplifier 3 (Op Amp 3) and Shared ADC Core | Differential current feedback from shunt resistor Rsh2 connects to non-inverting and inverting inputs of Op Amp 3 through input resistors. |
| OA3IN- | 22 | OA3IN-/AN13/CMP1B/ISRC0/RP49/PMA7/RC1 | ||
| IB | 18 | OA3OUT/AN4/CMP3B/IBIAS3/RA4 | Op Amp 3 Output, which is an amplified phase B current. For the output to be available, configure and enable Op Amp 3. | |
| Overcurrent Detection and Fault Output | ||||
| IBUS | 17 | DACOUT1/AN3/CMP1C/RA3 | High Speed Analog Comparator 1(CMP1) and DAC1 | Amplified Bus current is further filtered before connecting to the positive input of CMP1 for overcurrent detection. The over-current threshold is set through DAC1. The comparator output is internally available as a fault input of the PWM generators to shut down PWMs without CPU intervention. |
| Voltage Feedback | ||||
| V_BUS | 13 | AN12/ANN0/RP48/RC0 | Shared ADC Core | DC Bus voltage feedback |
| V_A | 47 | PGC1/AN11/RP41/SDA1/RB9 | Phase A voltage feedback | |
| V_B | 46 | PGD1/AN10/RP40/SCL1/RB8 | Phase B voltage feedback | |
| V_C | 45 | AN2/CMP3A/RP39/SDA3/RB7 | Phase C voltage feedback | |
| Servo Connector/External PWM/ADC (J2) | ||||
| AD_PWM_IN1 | 30 | AN19/CMP2C/RP75/PMA0/PMALL/PSA0/RD11 | Shared ADC Core | Analog/PWM Speed Command |
| AD_PWM_IN2 | 27 | AN15/CMP2A/IBIAS2/RP51/PMD11/PMA11/RC3 | ||
| UART_PWM | 21 | RP76/RD12 | GPIO with Peripheral Pin Select | Telemetry Data Output |
| Debug Interface (J3) | ||||
| DEBUG_RX | 32 | AN16/ISRC2/RP55/PMD8/PMA8/RC7 | Remappable Function of I/O and UART | These signals are connected to Header J3 to interface UART serial communication. |
| DEBUG_TX | 31 | AN18/CMP3C/ISRC3/RP74/PMD9/PMA9/RD10 | ||
| CAN Interface (J4) | ||||
| CANL | 49 | CAN Bus Low Line | Integrated CAN transceiver (U9C) of dsPIC33CDVC256MP506; this is Part C of the dsPIC33CDVC256MP506. | Refer to the data sheet for more details. |
| CANH | 50 | CAN Bus High Line | ||
| General Purpose IO Auxiliary and Reserved Pins and Test Points | ||||
| AUX1 | 28 | OSCI/CLKI/AN5/RP32/PMD10/PMA10/RB0 | dsPIC DSC pins for general purpose | These signals are routed to test pads to facilitate user interface connections. |
| AUX2 | 36 | RP56/ASDA1/SCK2/RC8 | ||
| AUX3 | 37 | RP57/ASCL1/SDI2/RC9 | ||
| RSVD1 | 39 | RP72/SDO2/PCI19/RD8 | ||
| RSVD2 | 38 | RP73/PCI20/RD9 | ||
| TEMP | 24 | AN17/ANN1/IBIAS1/RP54/PMD12/PMA12/RC6 | Shared ADC Core | This pin is for external temperature sensing. |
| TP12 | 10 | RB14/PWM1H | Test points on the dsPIC® DSC pins | This pin serves as a test point for debugging. |
| TP13 | 53 | RB10/PWM3H | ||
| TP14 | 54 | RB13 | ||
| TP17 | 29 | OSCO/CLKO/AN6/RP33/PMA1/PMALH/PSA1/RB1 | ||
| TP19 | 11 | RB15/PWM1L | ||
| Integrated Gate Driver (U9B) of dsPIC33CDVC256MP506 | ||||
| VDC | 7 | HVDD | Integrated Gate Driver (U9B) of dsPIC33CDVC256MP506; this is Part B of the dsPIC33CDVC256MP506. | Refer to the data sheet for more details. |
| PGND | 5, 66 | HVSS | ||
| 9 | CAP1 | |||
| 8 | CAP2 | |||
| DRV_VBOOT | 4 | VBOOT | ||
| DRV_VREG | 6 | VREG | ||
| DRV_WAKE | 55 | WAKE | ||
| 58 | VBA | |||
| 61 | VBB | |||
| 64 | VBC | |||
| PHASE_A | 56 | PHA | ||
| PHASE_B | 59 | PHB | ||
| PHASE_C | 62 | PHC | ||
| 57 | HSA | |||
| 60 | HSB | |||
| 63 | HSC | |||
| 1 | LSA | |||
| 2 | LSB | |||
| 3 | LSC | |||
| Integrated CAN FD Transceiver (U9C) | ||||
| 50 | CANH | Integrated CAN FD Transceiver (U9C) of dsPIC33CDVC256MP506; this is Part C of the dsPIC33CDVC256MP506. | Refer to the data sheet for more details. | |
| 49 | CANL | |||
| 43 | CAN_RXD | |||
| 48 | CAN_VDD | |||
| 51 | CAN_VSS | |||
| 67 | N/C | |||