3.2.2.1 Connectors

Neutral Connector (for an AC grid), J1.

Table 3-1. Neutral Connector (for an AC grid), J1
Pin	Signal Name	Description
1	N	Neutral (VN in PCB)
2	N	Neutral (VN in PCB)

Line Voltage Connector (for an AC grid), J2.

Table 3-2. Line Voltage Connector (for an AC grid), J2
Pin	Signal Name	Description
1	L1	Line 1 (V1 in PCB)
2	L2	Line 2 (V2 in PCB)

DC Input Connector, J3.

Current Sensor Input 1 Connector (for Line 1 voltage), J10.

Table 3-4. Current Sensor Input 1 Connector, J10
Pin	Signal Name	Description
1	IN1	Current channel 1, negative input
2	IP1	Current channel 1, positive input

Current Sensor Input 2 Connector (for Line 2 voltage), J11.

Table 3-5. Current Sensor Input 2 Connector, J11
Pin	Signal Name	Description
1	IN2	Current channel 2, negative input
2	IP2	Current channel 2, positive input

Micro-B Female USB Connector, J12.

Isolated Pulse Outputs Connectors, J13 and J14.

Table 3-7. Isolated Pulse Outputs Connector, J13
Pin	Signal Name	Description
1	CF1-	Negative isolated pulse
2	CF1+	Positive isolated pulse

Table 3-8. Isolated Pulse Outputs Connector, J14
Pin	Signal Name	Description
1	CF2-	Negative isolated pulse
2	CF2+	Positive isolated pulse

JTAG/SWD 10-pin Dual Row Connector for PIC32CXMTSH, J17.

Table 3-9. SWD Connector, J17
Pin	Mnemonic	Description
1	VCC	This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from V_CC on the target board and must not have a series resistor
2	SWDIO/TMS	Serial Wire Input Output/Test Mode Select. JTAG mode set input of target CPU. This pin should be pulled up on the target. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal
3	GND	Ground
4	SWCLK/TCK	Serial Wire Clock/Test Clock. JTAG clock signal to target CPU (output timing signal, for synchronizing test logic and control register access)
5	GND	Ground
6	SWO/TDO	Serial Wire Output / Test Asynchronous Data Out from target CPU
7	KEY	—
8	NC/TDI	Not Connected/Test Data Input. JTAG data input of target CPU (serial data output line, sampled on the rising edge of the TCK signal). It is recommended that this pin is pulled to a defined state on the target board
9	GND Detect	Ground
10	nRESET	JTAG Reset (active-low output signal that resets the target). Output from the JTAG debug probe to the Reset signal on the target JTAG port. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection

Xplained PRO Power Header, J19.

Xplained PRO Extension Header, J20.

Table 3-11. Xplained PRO Extension Header, J20
Pin	Mnemonic	Description
1	—	Test Point
2	GND	Reference Ground
3	ADC+	Analog to digital converter, alternatively positive part of differential ADC
4	ADC-	Analog to digital converter, alternatively negative part of differential ADC
5	GPIO1	General purpose I/O
6	GPIO2	General purpose I/O
7	PWM+	Pulse width modulation, alternatively positive part of differential PWM
8	PWM-	Pulse width modulation, alternatively negative part of differential PWM
9	IRQ/GPIO	Interrupt request line and/or general purpose I/O
10	SS/GPIO	Serial select for SPI and/or general purpose I/O
11	TWD	I²C Data
12	TWCK	I²C Clock
13	RXD	UART Receiver
14	TXD	UART Transmitter
15	SS	SPI Chip Select
16	MOSI	SPI Host Output Client Input
17	MISO	SPI Host Input Client Output
18	SCK	SPI Clock
19	GND	Reference Ground
20	VCC	3.3V power for extension board

mikroBUS add-on Board Connector, J21.