5.1 Core Enhancements and Upgrades

The following table lists core enhancements and upgrades in Libero SoC v2025.2. For more information about updating a core version, see the section Updating a Core Version.

Table 5-1. Core Enhancements and Upgrades
Core2025.2 VersionStatusComments
PF_CCC2.2.222ProductionAdded fix for incorrect configurator-generated settings for PolarFire DLL in Phase Generation Mode.
PF_IO2.0.106ProductionAdded support for Delay mode feature with two options, Narrow and Wide, with delay tap range support of 0-127 and 0-255, respectively.
PF_IOD_GENERIC_RX2.1.116ProductionAdded support for fractional clock parallel data in fractional dynamic mode.
PF_IOD_OCTAL_DDR2.0.113ProductionImproved configurability, timing, and simulation accuracy for IOD Octal DDR. See the IOD Octal DDR Enhancements section.
PF_RGMII_TO_GMII1.3.111ProductionRepackaged to include the latest PF_IOD_GENERIC_RX version.
PF_SRAM_AHBL_AXI1.2.115ProductionHigh-reliability options added for PF_SRAM_AHBL_AXI with CoreAHBLSRAM_PF v3.0 and CoreAXI4SRAM v3.0. See the Enhanced PF_SRAM_AHBL_AXI with High-Reliability Options section.
PF_SYSTEM_SERVICES3.0.104ProductionHigh-reliability options added for PF_SYSTEM_SERVICES with CoreSysServices_PF v4.0. See the Enabled Fault Tolerance for PF_SYSTEM_SERVICES section.
PF_SPACEWIRE_RX_PHY1.0.110ProductionAdded the option to expose the Failsafe ODT_EN port for the SPACEWIRE_RX core interface. See the Added Failsafe ODT_EN Support for SPACEWIRE_RX section.
RTG4_SRAM_AHBL_AXI1.0.123ProductionHigh-reliability options added for RTG4_SRAM_AHBL_AXI with CoreAHBLSRAM_PF v3.0 and CoreAXI4SRAM v3.0. See the Enhanced RTG4_SRAM_AHBL_AXI with High-Reliability Options section.