3.2 IOD Octal DDR Enhancements
(Ask a Question)Libero SoC v2025.2 introduces several enhancements to improve configurability, timing, and simulation accuracy for IOD Octal DDR:
- PLL_POWERDOWN_N is now exposed by default to facilitate enabling of the PLL only when the REF_CLK input is stable.
- Added DQS_DELAY_TAP options up to 139 for expanded tuning flexibility.
- Any tap value in the full range of 1–255 allowed for the DQS delay setting.
- Added support for non-integer clock frequency entry to accommodate a wider range of design requirements.
- Improved timing constraints generation to ensure better coverage and timing robustness.
- Improved performance by inserting two-stage pipeline and register duplication for Async-assert, Sync-deassert Reset.