1.1.2.5 Enhanced Simulation Support for Processor BFM and Tiny QoS AXI Initiator
(Ask a Question)The mss_cpu_core can access the non-cache region of MSS DDR through the M14 port of the AXI switch. To mimic the processor behavior during simulation, you can choose to enable either the Processor BFM for the mss_cpu_core or a tiny QoS AXI Initiator, depending on your verification needs.