1.1.4 ADC Conversion Clock
The ADC conversion clock is used to generate conversion timing. The conversion clock source comes from either the system clock source (FOSC) or the dedicated ADCRC clock source. The ADC Clock Selection (CS) bit of the ADC Control Register 0 (ADCON0) determines which clock source is used by the module.
When the FOSC is selected as the conversion clock source, the conversion clock frequency is determined by the ADC Conversion Clock Select (CS) bits of the ADC Clock Selection (ADCLK) register. The ADCLK register acts as a prescaler for the FOSC, dividing the clock to a frequency that meets the ADC clock period (TAD) specification. A TAD cycle is defined as the time to complete a single bit conversion. Table 1-1 illustrates the possible TAD periods based on the ADCLK configurations and system clock frequencies.
| ADCLK CS<5:0> | Device Frequency (FOSC) | ||||||
|---|---|---|---|---|---|---|---|
| 64 MHz | 32 MHz | 20 MHz | 16 MHz | 8 MHz | 4 MHz | 1 MHz | |
| TAD | TAD | TAD | TAD | TAD | TAD | TAD | |
000000 (FOSC/2) | 31.25 ns | 62.5 ns | 100 ns | 125 ns | 250 ns | 500 ns | 2 us |
000001 (FOSC/4) | 62.5 ns | 125 ns | 200 ns | 250 ns | 500 ns | 1 us | 4 us |
000010 (FOSC/6) | 93.75 ns | 187.5 ns | 300 ns | 375 ns | 750 ns | 1.5 us | 6 us |
000011 (FOSC/8) | 125 ns | 250 ns | 400 ns | 500 ns | 1 us | 2 us | 8 us |
| ··· | ··· | ··· | ··· | ··· | ··· | ··· | ··· |
000111 (FOSC/16) | 250 ns | 500 ns | 800 ns | 1 us | 2 us | 4 us | 16 us |
| ··· | ··· | ··· | ··· | ··· | ··· | ··· | ··· |
001111 (FOSC/32) | 500 ns | 1 us | 1.6 us | 2 us | 4 us | 8 us | 32 us |
| ··· | ··· | ··· | ··· | ··· | ··· | ··· | ··· |
011111 (FOSC/64) | 1 us | 2 us | 3.2 us | 4 us | 8 us | 16 us | 64 us |
| ··· | ··· | ··· | ··· | ··· | ··· | ··· | ··· |
111111 (FOSC/128) | 2 us | 4 us | 6.4 us | 8 us | 16 us | 32 us | 128 us |
When the dedicated ADCRC clock is selected as the ADC conversion clock source, the conversion clock operates at a nominal 600 kHz clock frequency. The ADCRC can be used in applications that do not require high speed conversions. The ADCRC allows the ADC to operate in Sleep mode, which is great for low-power applications. The ADCRC produces a range of TAD times which vary from 1.0 to 3.0 us.
To ensure correct conversion results, the appropriate TAD requirements must be met. Typically, one TAD is required for each bit conversion, with an additional two TAD cycles required to cover the time elapsed from the disconnection of the sampling capacitor to when the conversion actually begins (see figure below).
It is important to note that when using FOSC as the clock source, any changes in the FOSC frequency will also change the ADC clock frequency, which may cause erroneous conversion results. The FOSC allows for faster TAD cycles, which result in faster conversion times, but cannot operate in Sleep mode.
