11.2 Timing Diagrams for Synchronous Communications

Figure 11-1. Bus Timing
???
Figure 11-2. Write Cycle Timing
???
Note: The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal clear/write cycle
Figure 11-3. Data Validity
???
Figure 11-4. Start and Stop Definition
???
Figure 11-5. Output Acknowledge
???