8.7.2 Design Layout Recommendations

When designing the QSPI interface, consider the following recommendations:

  • Apply impedance control of 50 Ohms on the clock and data interfaces.
  • Match signal lengths to within 10 mils. Affected PIOs in the example above are PB19 to PB24.
  • Place the clock line (PB19) at least three times the trace width away from other signals for noise immunity.
  • Place data signals at least two times the trace width away from any other data traces.
  • Place data signals at least one trace width away from any copper plane.
Figure 8-11. QSPI Layout Example