The following figure shows the default memory mapping of the Arm Cortex-M
core.
Figure 7-1. Cortex-M Memory Mapping Table 7-1. Code Area Base Address End Address Memory Size Comment 0x00000000 – Boot Memory 16 Mbytes ROM Code 0x01000000 – Internal Flash 16 Mbytes Code - Non Cached 0x02000000 0x0201FFFF Reserved – – 0x02020000 – CPKCC ROM 64 Kbytes – 0x02030000 0x0203FFFF Reserved – – 0x02031000 0x02031FFF CPKCC RAM – – 0x02032000 0x03FFFFFF Undefined (Abort) – – 0x04000000 – QSPI MEM 32 Mbytes Code - Non Cached 0x06000000 – QSPI MEM AESB 32 Mbytes Code through AESB - Non Cached 0x08000000 0x0FFFFFFF Undefined (Abort) – – 0x10000000 – Undefined (Abort) 16 Mbytes – 0x11000000 – Internal Flash 16 Mbytes Code - Cached 0x12000000 – Undefined (Abort) 16 Mbytes – 0x13000000 – Undefined (Abort) 16 Mbytes – 0x14000000 – QSPI MEM 32 Mbytes Code - Cached 0x16000000 0x1FFF9FFF QSPI MEM AESB 32 Mbytes Code through AESB - Cached 0x1FFFA000 0x1FFFBFFF DTCM 8 Kbytes – 0x1FFFC000 0x1FFFFFFF ITCM 16 Kbytes –
Table 7-2. SRAM Area Base Address End Address Memory 0x20000000 0x2007FFFF SRAM0(1)
Note:
In a small product configuration, depending on the real size of the embedded SRAM0,
the expected responses when accessing SRAM0 area are:accessing 256 Kb/half upper
area -> ABORT (SRAM0 size < 512 Kb) accessing 2nd quarter (128 to
256 Kb) -> ABORT (SRAM0 size < 256 Kb Table 7-3. AHB-to-APB Bridges Base Address Instance 0x40000000 BRIDGE 0 0x44000000 BRIDGE 2 0x46000000 BRIDGE 3 0x48000000 BRIDGE 1 0x4A000000 BRIDGE 4
Table 7-4. BRIDGE 0
Peripheral Mapping Base Address Peripheral Comments 0x40000000 FLEXCOM0 0x40004000 FLEXCOM1 0x40008000 FLEXCOM2 0x4000C000 FLEXCOM3 0x40010000 FLEXCOM4 0x40014000 FLEXCOM5 0x40018000 FLEXCOM6 0x4001C000 FLEXCOM7 0x40020000 QSPI 0x40024000 ADC 0x40028000 ACC 0x40034000 MEM2MEM0 0x40038000 TC0 0x4003C000 TC1 0x40040000 TC2 0x40044000 MATRIX1 0x40048000 PIOA, PIOB, PIOC 0x4004C000 Reserved 0x40050000 System Controller 0x40054000 Reserved
Table 7-5. BRIDGE 1 Peripheral Mapping Base Address Peripherals Comments 0x48004000 MEM2MEM1 0x48008000 TC3 0x4800C000 PIOD 0x48010000 UART 0x48018000 MCSPI 0x4801C000 PWM 0x48020000 MATRIX3 0x48028000 Reserved
Table 7-6. BRIDGE 2 Peripheral Mapping Base Address Peripherals Comments 0x44000000 AES 0x44004000 AESB 0x44008000 SHA 0x4400C000 TRNG 0x44010000 ICM 0x44014000 Reserved
Table 7-7. BRIDGE 3 Peripheral Mapping Base Address Peripherals Comments 0x46000000 CPKCC 0x46004000 MATRIX0 0x46008000 CMCC0 0x4600C000 CMCC1 0x46010000 Reserved 0x460E0000 SEFC0 0x460E0200 SEFC1 0x46000000 Reserved 0x460E0400 Reserved 0x46800000 PMC 0x46800200 Reserved 0x46800400 Reserved
Table 7-8. BRIDGE 4 Peripheral Mapping Base Address Peripherals Comments 0x4A000000 MATRIX2 0x4A004000 Reserved
Table 7-9. System Controller Base Address Peripherals Comments 0x40050000 Reserved 0x40050200 CHIPID 0x40050400 SFR 0x40050600 SFRBU 0x40050800 Reserved 0x40052000 SYSC
Table 7-10. External SRAM Base Address Peripherals Comments 0x60000000 to0x9FFFFFFF
Undefined (Abort)
Table 7-11. External Peripherals Base Address Peripherals Comments 0xA0000000 Undefined 0xA1000000 Internal Flash Write Strongly ordered Alias address for Flash
Controller Page Buffer 0xA2000000 Undefined 0xA3000000 Undefined 0xA4000000 Undefined (Abort)
