52 Revision History

Revision C - 03/2026

The following changes were implemented for this revision:


Section	Changes
Mechanical Characteristics	Updated figures.

Rev. B - 11/2022

Note: Microchip is in the process of implementing inclusive language in our documentation. During this update, you may see the old terms and the new terms in our documentation text. We apologize for any confusion.


Section	Changes
Minor editorial changes throughout.
Pinout and Multiplexing	Corrected pin 62 namein table 128-pin EP-TQFP Multiplexing.
Input/Output Lines	Shutdown (SHDN) Pin: corrected pin name.
Input/Output Lines	Flash Memory Hardware ERASE Signal: updated.
ROM Code and Boot Strategies	GPNVM Bits Overview: updated table.
Supply Controller (SUPC)	SUPC_SR: index 12 now 'reserved'.
Clock Generator	PLL Controls: updated.
Power Management Controller (PMC)	Block Diagram: updated.
Special Function Registers (SFR)	Register Write Protection: list of registers updated. Register Summary: offset 0xA0 now reserved (was Core Debug Configuration Register). SFR_PWM_DEBUG: index 1 now ‘reserved’ (was CORE1)
Chip Identifier (CHIPID)	Chip ID Registers: updated table.
Flexible Serial Communication Controller (FLEXCOM)	Throughout: Deleted references to Host High-Speed mode. Bus Clear Command, FIFO Pointer Error, FLEX_TWI_CR: modified Sniffer Mode: updated Sniffer description. FLEX_TWI_SMR: updated BSEL description.
Quad Serial Peripheral Interface (QSPI)	Corrected clock name from GCK to GCLK throughout.
Analog-to-Digital Converter (ADC) Controller	ADC_MR: updated reset value.
Analog Comparator Controller (ACC)	ACC_ISR: updated reset value.
True Random Number Generator (TRNG)	TRNG_WPSR: modified SWETYP description (value 5).
Pulse Width Modulation Controller (PWM)	Fault Protection: figure updated.
Electrical Characteristics	VDD3V3 Power-On-Reset: corrected unit in table. Analog Comparator Characterisitics: corrected unit in table.

Rev. A - 03/2022

First Issue.