19.14.8 SCANCON0

Scanner Access Control Register 0

Note:

Setting EN = 0 does not affect any other register content.
This bit can be cleared in software. It is cleared in hardware when LADR > HADR (and a data cycle is not occurring) or when CRCGO = 0.
CRCEN and CRCGO bits must be set before setting the SGO bit.
Trigger Mode source selection can be set using the SCANTRIG register.
This bit will read '0' when the SCANDPS bit is clear.

Name:	SCANCON0
Offset:	0x1C92


Bit	7	6	5	4	3	2	1	0
	EN	SGO	BUSY	DABORT	INTM	LOAD	MD[1:0]
Access	R/W	R/W/HC	R	R	R/W	R	R/W	R/W
Reset	0	0	0	1	0	0	0	0

Bit 7 – EN Scanner Enable⁽¹⁾

Value	Description
1	Scanner is enabled
0	Scanner is disabled

Bit 6 – SGO Scanner GO^(2,3)

Value	Description
1	Begin scanner operations
0	Scanner operations will not occur

Bit 5 – BUSY Scanner Busy Indicator

Value	Description
1	Scanner cycle is in process
0	Scanner cycle is compete (or never started)

Bit 4 – DABORT Scanner Abort Signal

Value	Description
1	SCANLADR points to an invalid NVM address, or the CRC is disabled
0	SCANLADR points to a valid NVM address and the CRC is enabled

Bit 3 – INTM Scanner Interrupt Management Mode Select

Value	Name	Description
1	MD = ‘`00`’, ’`01`’, or ‘`11`’	Scan operations are paused during the interrupt response and resume after the interrupt has been serviced
0	MD = ‘`00`’ or ‘`11`’	Interrupt operations are stalled each time the scanner accesses memory and resume between scan operations
0	MD = ‘`01`’	Interrupt operations are stalled until SGO is cleared by hardware
x	MD = ‘`10`’	This bit is ignored

Bit 2 – LOAD Scanner Data Load to CLB Indictor⁽⁵⁾

Value	Description
1	Scanner is in the process of loading data to the CLB
0	Scanner data load to the CLB is complete (or never started)

Bits 1:0 – MD[1:0] Scanner Memory Access Mode Select⁽⁴⁾

Value	Description
11	Trigger Mode
10	Peek Mode
01	Burst Mode
00	Concurrent Mode

Setting EN = 0 does not affect any other register content. This bit can be cleared in software. It is cleared in hardware when LADR > HADR (and a data cycle is not occurring) or when CRCGO = 0. CRCEN and CRCGO bits must be set before setting the SGO bit. Trigger Mode source selection can be set using the SCANTRIG register. This bit will read '0' when the SCANDPS bit is clear.