42.3.1 Supply Voltage

Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.Min.Typ.†Max.UnitsConditions
Supply Voltage
D002VDD1.8—5.5VFOSC ≤ 16 MHz
D002A2.5—5.5VFOSC > 16 MHz
RAM Data Retention(1)
D003VDR1.7——VDevice in Sleep mode; on VDD domain
Power-on Reset Release Voltage(2)
D004VPOR—1.6—VBOR and LPBOR disabled(3); on VDD domain
Power-on Reset Rearm Voltage(2)
D005VPORR—1—VBOR and LPBOR disabled(3); on VDD domain
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006*SVDD0.05——V/msBOR and LPBOR disabled(3); on VDD domain
D006A*——1.2V/μs1.8V ≤ VDD ≤ 5.5V

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
  2. See the following figure, POR and POR REARM with Slow Rising VDD.
  3. See "Reset, WDT, Oscillator Start-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications" for BOR and LPBOR trip point information.
Figure 42-2. POR and POR Rearm with Slow Rising VDD
Note:
  1. When NPOR is low, the device is held in Reset.
  2. TVLOW 2.7 μs typical.
  3. TPOR 1 μs typical.