29.4.1 Programmable Input Edge Detectors

The output of each of the 16 input selection latches is fed into programmable edge detectors. CLB input synchronization and edge detection is configured using the Microchip CLB Synthesizer. The Microchip CLB Synthesizer configuration determines whether the edge detectors are positive edge-triggered, negative edge-triggered, or bypassed completely, and also determines whether the output of the edge detectors are synchronous or asynchronous to the CLB clock.

Figure 29-3. Edge Detector Block Diagram
Note:
  1. These selections are configured using the Microchip CLB Synthesizer.
Important: When input edge synchronization is selected, the edge detector circuitry is reset by module hardware automatically.

The illustrations below show examples of edge detector operation.

Important: If any of the BLEs are programmed to use the output flip-flop, care must be taken so that the asynchronous input does not cause the BLE flop to go into metastability.
Figure 29-4. Asynchronous Operation Without Edge Detection (Edge Detector is Bypassed)

In Figure 29-4, the non-inverted CLB Input Selection signal bypasses the edge detector and is used as an asynchronous BLE Input Selection.

Figure 29-5. Asynchronous Operation With Positive Edge Detection

In Figure 29-5, the non-inverted CLB Input Selection signal passes through the edge detector and is used as an asynchronous BLE Input Selection. The edge detector circuit is reset by module hardware.

Figure 29-6. Asynchronous Operation With Negative Edge Detection

In Figure 29-6, the inverted CLB Input Selection signal passes through the edge detector and is used as an asynchronous BLE Input Selection. The edge detector circuit is reset by module hardware.

Figure 29-7. Synchronous Operation Without Edge Detection (Edge Detector is Bypassed)

In Figure 29-7, the non-inverted CLB Input Selection signal bypasses the edge detector and is synchronized to the CLB clock.

Figure 29-8. Synchronous Operation With Positive Edge Detection

In Figure 29-8, the non-inverted CLB Input Selection signal passes through the edge detector and is synchronized on the rising edge of the CLB clock. The edge detector circuit is reset by module hardware.

Figure 29-9. Synchronous Operation With Negative Edge Detection

In Figure 29-9, the inverted CLB Input Selection signal passes through the edge detector and is synchronized on the rising edge of the CLB clock. The edge detector circuit is reset by module hardware.