29.4 CLB Module Inputs

The CLB module inputs are selectable through the Microchip CLB Synthesizer. The Microchip CLB Synthesizer can configure 16 inputs with optional clock synchronizers, each of which may receive an input signal from one of up to 40 selectable inputs as shown in the CLB Module Inputs table.

Table 29-1. CLB Module Input Signal Sources
Value	Description
`111111-101000`	Reserved
`100111`	V_SS
`100110`	CLKR
`100101`	PWM2S1P2_OUT
`100100`	PWM1S1P2_OUT
`100011`	TMR4_Postscaled_OUT
`100010`	TMR3_overflow_OUT
`100001`	SOSC⁽¹⁾
`100000`	TX2
`011111`	HLVD OUT bit
`011110`	SCK2
`011101`	SDO2
`011100`	C2_OUT
`011011`	C1_OUT
`011010`	CLBSWIN Write Hold (BUSY status bit = `'1'`)
`011001`	SCK1
`011000`	SDO1
`010111`	TX1
`010110`	CLC4_OUT
`010101`	CLC3_OUT
`010100`	CLC2_OUT
`010011`	CLC1_OUT
`010010`	IOCIF
`010001`	PWM2S1P1_OUT
`010000`	PWM1S1P1_OUT
`001111`	CCP2_OUT
`001110`	CCP1_OUT
`001101`	TMR2_Postscaled_OUT
`001100`	TMR1_overflow_OUT
`001011`	TMR0_overflow_OUT
`001010`	ADCRC⁽¹⁾
`001001`	EXTOSC⁽¹⁾
`001000`	MFINTOSC (32 kHz)⁽¹⁾
`000111`	MFINTOSC (500 kHz)⁽¹⁾
`000110`	LFINTOSC⁽¹⁾
`000101`	HFINTOSC⁽¹⁾
`000100`	F_OSC
`000011`	CLBIN3PPS
`000010`	CLBIN2PPS
`000001`	CLBIN1PPS
`000000`	CLBIN0PPS

Note:

Oscillator sources are not automatically enabled when selected as an input to the CLB module. If no additional peripherals are using the selected oscillator source, the source may be enabled through the OSCEN register (see the Oscillator Module (With Fail-Safe Clock Monitor) section).