1.5.2 RTG4, SmartFusion2, and IGLOO2

In the Libero SoC v2025.1 release, the RTG4FCCCECALIB core configuration GUI has been enhanced. Frequency fields in the Basic and Advanced tabs are now grayed out and disabled when the requested mode does not use the PLL or GPDs.

For example, when using the Clock Recovery Circuit as the source for a specific CCC output, the reference clock and requested output frequency fields are disabled. Similarly, when the PLL is bypassed, such as when using the internal 50MHz RC Oscillator or a direct CCC input as the source for a specific CCC output, the unused Exact Frequency checkbox is disabled.

The Libero SoC 2025.1 release enhances the GUI option in Serdes configurator to automatically compute correct Signal Integrity register values when the protocol of lane is XAUI/EPCS for SmartFusion2, IGLOO2, and RTG4 families.

Libero SoC v2025.1 adds support to propagate chip-level hardwired connections (for example, OSC_RC50MHZ, CCC to DELCAL) to the top module in block mode for SmartFusion2, IGLOO2, and RTG4 devices. This support resolves previous compile and layout issues specific to block design methodology.

The Libero SoC 2025.1 release adds parameters to eNVM simulation model that allow users to account for silicon delays stated in the device datasheet.

Libero SoC v2025.1 adds SVF programming support for SmartFusion2 and IGLOO2 devices.

The Libero SoC 2025.1 release enables the System Controller Suspend Mode project setting used in the design bitstream to be a part of all reports for the following tool actions for RTG4 devices:

• Generate Bitstream
• Export Bitstream
• Export FlashPro Express job
• Run PROGRAM action
• FlashPro Express when running PROGRAM action