1.5.1 PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC

The Libero SoC v2025.1 release includes updates to support additional configurations for 64b6xb PCS mode. The new Gear Box option allows users to independently enable the following options for 64B66B / 64B67B modes:

• Scrambler/descrambler: This option can include or bypass the embedded scrambled/descrambler.
• Disparity (64b67b only)
• BER monitor state machine
• 32-bit data width

Starting with the Libero v2025.1 release, the FMAX for OCTAL_SPI IOD interfaces is increased from 400 Mbps to 500 Mbps for STD and -1 for all the GPIO and HSIO banks.

Starting with the Libero SoC v2025.1 release, Libero I/O editor support has been enhanced to add 3 mA output drive for SUBLVDS25 and SUBLVDS33 drive strength settings.

Starting with the Libero SoC v2025.1 release, the PF_IO configurator enables the clock edge selection for the RX/TX/OE registers for both rising and falling clock edges.

Libero SoC v2025.1 introduces enhancements to I/O delays for QDR and SpaceWire interfaces using LVDS 2.5V, HSTL 1.2V, and 1.5V standards. These improvements provide more accurate delay estimates for applicable designs.

Libero SoC v2025.1 adds support to automatically repair hold violations for source-sync TX interfaces during Place and Route with Repair Minimum Delay Violations enabled. In some low hold violation situations, the repair min-delay violations process checks whether tap delay is OFF, in which case the repair process starts from tap delay 0 instead of expiring without taking any action.

Libero SoC v2025.1 clarifies I/O register usage details in the Compile and Layout reports.

Starting with the Libero SoC v2025.1 release, the unused condition for some package pins has been updated.

Starting with the Libero SoC v2025.1 release , the I/O Bank report section has been updated to add auto-calibration information for all PolarFire and PolarFire SoC devices.

With the Libero SoC v2025.1 release, projects targeting PolarFire family FPGA and SoC device part numbers offered in MIL or automotive T2 temperature grade now include a Project Settings option for selecting the IND range for Analysis Operating Conditions used by static timing and power analysis. This enhancement allows designers using MIL or T2 devices in systems that do not operate beyond the IND range to analyze static timing and power at more applicable conditions.

Starting with the Libero SoC v2025.1 release, SPI-Flash programming support has been added for the space-grade MRAM part number, AS302G208-0108X0MCEY, from Avalanche Technology.

The Libero SoC 2025.1 release has the following updates and enhancements to PolarFire Simulation models and addresses a few bugs in simulations:

• LSRAM ECC error injection: The PF_TPSRAM configurator now supports ECC error injection during pre-synthesis simulation by setting a defined mask address, as described in the PolarFire Family Fabric User Guide.
• PF_IOD_GENERIC_RX: Simulation of L0_LP_DATA and L0_LP_DATA_N at high-speed data transition
• PF_IOD_TX_CCC: Updated 3.5 clock ratio
• Added post-layout simulation for I/O registers with SDF
• IOREG BA Simulation Support for inverted clocks with Neg edge register values

Libero SoC v2025.1 introduces MSS DDR I/O training results,a new feature to SmartDebug.

This release also adds the following enhancements:

• Signal integrity settings persistence
• XCVR eye monitor: Persistent eye plot
• Fabric DDR I/O margin training results