11.5 New Silicon Features and Enhancements

Libero SoC v2021.1 provides an sNVM client for Boot mode2 and an eNVM client for Boot mode3.

These clients enable the generation of a complete programming file for applications using each of these Boot modes.

Libero SoC v2021.1 introduces simulation support for the MSS Streaming interface in User Cryptoprocessor for PolarFire SoC “S” devices.

The streaming interface is used when Crypto operates in MSS, Shared-MSS, and Shared-Fab modes. The crypto block can be owned by either the Fabric or MSS, with ownership transferred during operation.

For more information, see the PolarFire SoC MSS Configurator User Guide.

Libero SoC v2021.1 enables an option to write and read MSS registers on the fly while operating from the SmartDebug GUI.

For more information, see the SmartDebug User Guide.

Libero SoC v2021.1 adds FPGA Hardware Breakpoint auto-instantiation (FHB) support for the RTPF500T/TS/TL/TLS devices.

For more information, see the SmartDebug User Guide.

Libero SoC v2021.1 extends the PolarFire Transceiver Enhanced Receiver Management (ERM) solution to add the incremental calibration options “On-Demand” and “On-Demand and First Lock.”

For more information, see the PolarFire FPGA Transceiver User Guide.

Libero SoC v2021.1 enables the REF_CLK output pin of PF_XCVR_REF_CLK to drive a fabric global net via a CLKINT instance.

For more information, see the PolarFire FPGA Transceiver User Guide.

Libero SoC v2021.1 introduces simulation capability of PolarFire Transceiver components at both post-synthesis and post-layout stages.

For more information, see the PolarFire FPGA Transceiver User Guide.

Libero SoC v12.6 introduced the ability to recalibrate I/Os on-demand for each bank.

Libero SoC v2021.1 allows an individual I/O to opt out of recalibration. I/O recalibration is sometimes required to account for delays or to compensate Vt performance impact.

In PDC or I/O Attribute Editor, select the Drive and Termination Impedance calibration codes from the lane (never changed after first PoR calibration) to opt out of the recalibration done from the fabric. Example:

- set_io -port_name A -USE_LANE_CALIB_CODE Yes

For more information, see the PolarFire FPGA User I/O User Guide and the UG0725: PolarFire FPGA Device Power-Up and Resets User Guide.

Libero SoC v2021.1 extends the PF_IO configurator to enable all possible combinations of I/O registers in both directions along with a dynamic schematic representation of the configured I/O.

The Compile report, I/O Editor, Pin report, and I/O Register Combining report also have been enhanced to include the source constraint information.

For more information, see the PolarFire FPGA User I/O User Guide.

Libero SoC v2021.1.adds a new P&R Pin report (pinrpt_boardlayout.csv) formatted into a table where users can filter selections or sort on any column.

For more information, see the Libero SoC Design Flow User Guide for PolarFire.

Libero SoC v2021.1 permits debugging of source synchronous timing margins for dynamically tuned PF_IOD_GENERIC_RX IP interfaces.

To support this feature, the SmartDebug main page for PolarFire designs shows a Debug IOD button when there is a PF_IOD_GENERIC_RX IP instance configured as Dynamic or Fractional Dynamic mode in the design. The button is not shown for designs where the IP is configured in modes other than the ones mentioned above. After the Instance is selected and Get Training Data is clicked, the tap delay values are shown for the CORERXIODBITALIGN IP instances that are used to train the instance selected. For the Libero SoC v2021.1 release, CORERXIODBITALIGN IP v2.2.100 is the latest version available.

For more information, see the SmartDebug User Guide for PolarFire.

Libero SoC v2021.1 adds bank group interleaving to the DDR4 interface to improve the throughput.

For more information, see the PolarFire FPGA Memory Controller User Guide.

Libero SoC v2021.1.introduces a new tool in the Design Flow that allows you to tune I/O attributes and external timing without needing to rerun Place and Route. Input is provided using a PDC file. From the Design Flow menu, double-click Edit Post Layout Design to open a file selection dialog box for selecting the input file.

In batch flow, you can issue the command edit_post_layout_design <input.pdc>.

The PDC file contains one or more invocations of two PDC commands:

• edit_io
• edit_instance_delay

For more information about these commands, see the PDC Command User Guide - PolarFire.

To assist you in knowing which instances can have delays updated by this tool, the Place and Route tool generates a new report file named <root>_delayinstance.rpt. This report has an Editable? column, with Yes and No values that indicate whether a delay parameter can be edited by this tool.

The PDC commands fail if the syntax is incorrect, the referenced instances do not exist, or the values are out of legal ranges. If the batch command fails, the layout state of the design does not change. If the batch command succeeds, the layout state changes to reflect the values in the PDC commands, pin report and delay instance report files are regenerated to reflect the latest values, and the downstream tools Verify Timing, Verify Power, Generate FPGA Array Data, and Generate Back Annotated Files are invalidated.

For more information, see the Libero SoC Design Flow User Guide for PolarFire.

Synplify Pro R-2020.09M-SP1-1 bundled with Libero SoC v2021.1 introduces a new directive to pair two 9x9 multiplications into a single MATH block.

Example:

module mult_simd(clk, din1, din2, din3, din4, dout1, dout2);
    parameter n = 1;
    input clk;
    input [8:0] din1, din2, din3, din4;
    output [17:0] dout1 /* synthesis syn_multstyle = "simd:1" */;
    output [17:0] dout2 /* synthesis syn_multstyle = "simd:1" */;
    reg [17:0] dout1;
    reg [17:0] dout2;
    always @( posedge clk )
    begin
        dout1 <= din1 * din2 ;
        dout2 <= din3 * din4 ;
    end
endmodule

For more information, see the Synplify Pro ME R-2020.09M-SP1-1 FPGA User Guide.

Libero SoC v2021.1 adds the capability to view post-layout routing in the Chip Planner tool.

For more information, see the Chip Planner User Guide.

Libero SoC v2021.1 adds partial programming capability to SPI Flash.

For more information, see the Libero SoC v2021.1 Design Flow User Guide for PolarFire.

PolarFire Transceiver components can source three clocks into the fabric:

• PF_XCVR_LANE#_TX_CLK
• PF_XCVR_LANE#_RX_CLK
• PF_REFCLK _FAB_REF_CLK

These clocks contain high-frequency jitter that Libero does not consider in the timing report and SmartTime. Therefore, users should add clock-uncertainty constraints to these clocks in their designs. The following table shows recommended values for clock uncertainty per clock, resource, and speed-grade.

The following example shows a clock-uncertainty constraint that can be added to the user's timing SDC file.

set_clock_uncertainty -setup 0.150 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_R } ]
set_clock_uncertainty -setup 0.175 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_R } ]
# TX_CLK and RX_CLK on Globals
set_clock_uncertainty -setup 0.300 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_G } ]
set_clock_uncertainty -setup 0.325 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_G } ]
# FAB_REF_CLK on Global
set_clock_uncertainty -setup 0.275 [get_clocks PF_DDR4_C0_0/CCC_0/pll_inst_0/OUT1]

The automatic management of these constraints will be added in a future release of Libero SoC.