11.4 Software Features and Enhancements

Libero SoC v2021.1 introduces a new Detect Clock Domain Crossings detection option for analyzing clock domain crossings (CDC) in the RTL design, detecting safe synchronizer circuits according to your specification, and implementing them in Place and Route (P&R). This option is available in the Synthesize Options dialog box and shown in the following figure.

A new report is generated by the Synplify Pro R-2020.09M-SP1-1 tool bundled with Libero SoC v2021.1 listing all CDC situations in the design. The generated CDC report will not contain any synchronizer circuits formed with macros instantiated from the catalog. The generated report, with the name <root_name>_cdc.csv, will be visible in the respective Synthesis node of the report view (Design > Reports). A summary of the placement of the safe synchronizer registers appears in the P&R log and SmartTime CDC report.

For more information, see the following documents:

• Libero SoC Design Flow User Guide for PolarFire
• Libero SoC v2021.1 Design Flow User Guide for RTG4, SmartFusion2, and IGLOO2

SmartTime CDC view in Libero SoC v2021.1 adds an indication of crossings where all paths have safe synchronizers. In addition, you can now cross-probe from this view to the Timing Report Explorer.

For more information, see the SmartTime User Guide.

The interactive Timing Report Explorer in Libero SoC v2021.1 enhances the expanded path view with a tree structure that is easy to navigate. In addition, you can cross-probe paths to the Chip Planner.

For more information, see the SmartTime User Guide.

Libero SoC v2021.1 introduces a new Components view that lists all configured core components, blocks, and SmartDesign components in a project.

To open the view, click View > Windows > Components. When you open the Component view, a tab in the left area of the Libero SoC lists all configured components and SmartDesigns in the project. Right-clicking a component in the Component view tab displays a menu that is similar to the one that appears when you right-click entries in the Components section of the Design Hierarchy. A component manifest is available for all the components in the view, and can be viewed and accessed by expanding the manifest tree under each component. The CoreName and Version columns show the appropriate information. The timestamp shown for Generation appears in the Date Generated column and gets updated when the component regenerates.

For more information, see the following documents:

• Libero SoC Design Flow User Guide for PolarFire
• Libero SoC v2021.1 Design Flow User Guide for RTG4, SmartFusion2, and IGLOO2

The SmartDesign canvas in Libero SoC v2021.1 enables the Connection mode by default. The canvas pans automatically when realizing a connection using the Connection mode.

For more information, see the SmartDesign User Guide.

Libero SoC v2021.1 provides an option to enable the multiple-file compilation unit (MFCU) for System Verilog, so that constructs defined in one compilation unit are visible in a different compilation unit.

Libero SoC v2021.1 improves the vectorless activity estimation in SmartPower and reduces its computation time significantly.

For more information, see the SmartPower User Guide.

Synplify Pro R-2020.09M-SP1-1 bundled with Libero SoC v2021.1 introduces a new TMR report that lists all of the registers mapped in the design to enable user confirmation that the syn_radhardlevel=tmr directive has been implemented. PolarFire, PolarFire SoC, SmartFusion2, and IGLOO2 support this report. The report is available in the Libero SoC Reports tab under Synthesis reports, and uses the naming format <root>_tmr.rpt.

This version also optimizes the TMR area of async-reset-async-set FFs.

For more information, see the Synplify Pro ME R-2020.09M-SP1-1 FPGA User Guide.

The Synplify Pro and Identify tools bundled in Libero SoC v2021.1 have been upgraded to version R-2020.09M-SP1-1.

Libero SoC already has a synthesis option to optimize for Low power all memory inferred in the design. Users can now change memory inference to low_power implementation on an individual instance using the following directive:

reg [19:0] mem [0:2047] /* synthesis syn_ramstyle = "low_power" */;

If the Low power option is enabled at the design level, you can now change memory inference to no_low_power implementation on an individual instance using the following directive:

reg [19:0] mem [0:2047] /* synthesis syn_ramstyle = "no_low_power" */;

Synplify Pro R-2020.09M-SP1-1 now flags warning messages for unconnected Input pins across the RTL hierarchy.

• W: CG184 : Removing wire <net_name>, as it has the load but no drivers
• W: CG781: Input <pin_name> on instance <inst_name> is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
• W: CG360: Removing wire <net_name>, as there is no assignment to it.
• E: FX114: Pin <pin_name> of instance <inst_name> is undriven. Assign a valid signal to this pin.

For more information, see the Synplify Pro ME R-2020.09M-SP1-1 FPGA User Guide.

Libero SoC v2021.1 introduces support for Red Hat Enterprise Linux 8 and CentOS 8.

For installation information, see the Libero SoC Linux Environment Setup User Guide.