9.5 New Silicon Features and Enhancements

9.5.1 PolarFire, RT PolarFire, and PolarFire SoC

9.5.1.1 Design Initialization Data and Memory Report

Libero SoC v2021.3 consolidates all configuration information into the Design Initialization and Memory report. Tie-off information about important input pins for unused blocks also has been added to this report.

For more information, see AC478: PolarFire FPGAs for Safety-Critical Applications.

9.5.1.2 External Timing Closure of IOD Interfaces

The Repair minimum delay violations option of Place & Route in Libero SoC v2021.3 has been enhanced for external timing closure of IOD interfaces. If an initial maximum delay analysis detects any external setup violation, the programmable I/O delays are adjusted by the subsequent passes of minimum delay repair.

9.5.1.3 XCVR ERM Enhancements to Improve Transceiver Robustness

The PF_XCVR_ERM core in Libero SoC v2021.3 improves the robustness of the Enhanced Receiver Management solution where, in rare cases, the link would drop and then restart.

9.5.1.4 PF_TAMPER SECURITY_LOCKDOWN

The PF_TAMPER core version in Libero SoC v2021.3 renames the port LOCKDOWN to SECURITY_LOCKDOWN. When upgrading designs containing a PF_TAMPER component from a prior release, reconnect the net to the new port.

9.5.1.5 PolarFire XCVR-Sourced Fabric Clocks and Jitter Compensation

The PolarFire XCVR can source three different clocks into the fabric:

  • TX_CLK
  • RX_CLK
  • REFCLK (FAB_REF_CLK)

These clocks contain high-frequency jitter that is not automatically considered by Libero in the timing report and SmartTime. It is recommended that users add clock-uncertainty constraints to these clocks in their design. The following table shows recommended values for clock uncertainty per clock, resource, and speed-grade.

Table 9-3. Recommended Values for Clock Uncertainty
Clock TypeSTD-1
FAB_REF_CLK on Global275 ps200 ps
FAB_REF_CLK on RegionalN/AN/A
TX_CLK_G on Global300 ps225 ps
TX_CLK_R on Regional225 ps150 ps
RX_CLK_G on Global325 ps250 ps
RX_CLK_R on Regional250 ps175 ps
The following example shows a clock-uncertainty constraint that uses a -1 speed grade.
set_clock_uncertainty -setup 0.150 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_R } ]
 
set_clock_uncertainty -setup 0.175 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_R } ]

The following example shows a clock-uncertainty constraint with STD speed grade.


# TX_CLK and RX_CLK on Globals
 
set_clock_uncertainty -setup 0.300 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_G } ]
 
set_clock_uncertainty -setup 0.325 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_G } ]
 
# FAB_REF_CLK on Global
 
set_clock_uncertainty -setup 0.275 [get_clocks PF_DDR4_C0_0/CCC_0/pll_inst_0/OUT1]

The automatic management of these constraints will be added in a future release of Libero SoC.

Note: It is also important to add the other required jitter sources as clock uncertainty into your design constraints. See the datasheet for the jitter to be added for components such as PLL, DLL, and RC Oscillator. For input pins that are direct or are inputs to the DLL (but not for a PLL), the input jitter on the clock input pin must also be added to your timing constraints.

9.5.2 PolarFire SoC

9.5.2.1 Device Check when Importing an MSS Component (CXZ) into Libero SoC

Libero SoC v2021.3 checks against the current project device settings when importing an MSS component (CXZ).

For more information, see the Libero SoC Design Flow User Guide .

9.5.2.3 Configure I/O States During JTAG Programming Tool Support

Libero SoC v2021.3 adds support for the Configure I/O States During JTAG Programming tool for PolarFire SoC devices.

For more information, see the Libero SoC Design Flow User Guide .

9.5.2.4 Invoke MSS Configurator from Libero SoC as Read-Only

In a PolarFire SoC project opened in Libero SoC v2021.3, you can now invoke the MSS configurator by double clicking on the MSS component under the Design Hierarchy pane to view the settings of the MSS in read-only mode. To change any setting, you must run the standalone MSS configurator outside of Libero.

For more information, see the Libero SoC Design Flow User Guide .

9.5.2.5 MSS Simulation Model Enhancements

Libero SoC v2021.3 enhances the MSS simulation model to add support for the following features:

  • DMA-type transfers between MSS and fabric
  • Fabric initiator accessing L2-LIM of MSS

For more information, see the Revision History topic in the PolarFire SoC FPGA MSS Simulation User Guide.

9.5.3 RTG4

9.5.3.1 SmartDebug FPGA Hardware Breakpoint Area Reduction

For RTG4 designs, Libero SoC v2021.3 reduces the area of the logic inserted for FPGA Hardware Breakpoint.