7.5 New Silicon Features and Enhancements

The PF_TAMPER IP core has been updated to latch the FLAGS[13] and RESET_REASON[4:0] outputs. This is required to maintain the IP outputs when using system controller suspend mode. To enable this feature, check the option Latch System Controller Outputs in the IP configuration dialog and connect the generated core’s CLK_FROM_RCOSC_160MHZ input port to the internal 160 MHz RCOSC.

RT PolarFire FPGAs have been validated to support SpaceWire operation at up to 300 Mbit/sec (STD speed grade) and 400 Mbit/sec (-1 speed grade) using a third-party SpaceWire controller IP core connected to the Libero SoC v2022.2 IP Catalog SpaceWire RX PHY core.

For more information, including recommended SpaceWire RX PHY IP core configurations and pin assignments when implementing SpaceWire receiver interfaces on RT PolarFire FPGAs, see the RT PolarFire FPGA User I/O Guide.

SmartBERT core (CoreSmartBERT) version 2.9 has been enhanced to support 10.3125 Gbps data rates.

Libero SoC v2022.2 performs additional checks (for example, matching a SPI Bitstream file target device with a Libero SoC target device) during SPI Bitstream client creation in the Configure Design Initialization Data and Memory tool when importing a SPI bitstream file generated from Libero SoC v2022.2.

Libero SoC v2022.2 adds an option to include eNVM client pages in digest check calculations as part of VERIFY_DIGEST action. For more information, see the eNVM Tab topic in the Libero SoC Design Flow User Guide and the Libero help documentation.

The SPPS flow has been extended and is now available on PolarFire SoC devices. This includes adding support for Job Manager and HSM-based bitstream generation flows on PolarFire SoC devices.

For more information, see the Secure Production Programming Solution (SPPS) and Job Manager User Guide .

The PFSOC_INIT_MONITOR core version 1.0.304 has been upgraded from Pre-production to Production.

For more information, see section Core Enhancements and Upgrades

The MSS configurator user interface has been enhanced to include a Speed Mode selection for the following peripherals:

• I2C
• SPI
• SD/SDIO
• EMMC

For more information, see the Standalone MSS Configurator User Guide for PolarFire SoC .

To prevent a configured MSS register values from being changed, the <libero project>/designer/<root>/<root>_init_config_lock_bits.txt file has been updated to support locking MSS registers.

Registers are unlocked by default and you can edit the generated file to lock the registers by specifying a value of 0. To apply the changes, use the Configure Register Lock Bits tool to source the modified file.

The PolarFire SoC MSS simulation model has been enhanced to support initialization of DDR memory. The DDR memory can be initialized with .mem file, which helps in many applications by allowing you to perform first AXI write transactions.

For more information, see the MSS Simulation User Guide for PolarFire SoC .

Added support for the new SPI-Flash device IS25LP128 from ISSI vendor.