2.2.3.1 Hardwired Clock—Using LVTTL 24 mA High Slew Clock I/O

  • External Setup

    = (tDP + tRD2 + tSUD) – tHCKL

    = (1.72 + 0.53 + 0.23) – 3.02 = –0.54 ns

  • Clock-to-Out (Pad-to-Pad)

    = tHCKL + tRCO + tRD1 + tPY

    = 3.02 + 0.67 + 0.45 + 2.99 = 7.13 ns