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Axcelerator Family FPGAs Datasheet
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2
Electrical Specifications
2.9
Axcelerator Clock Management System
2.9.6
Sample Implementations
Introduction
1
General Description
2
Electrical Specifications
2.1
Operating Conditions
2.2
Thermal Characteristics
2.3
I/O Specifications
2.4
Voltage-Referenced I/O Standards
2.5
Differential Standards
2.6
Module Specifications
2.7
Routing Specifications
2.8
Global Resources
2.9
Axcelerator Clock Management System
2.9.1
Physical Implementation
2.9.2
Functional Description
2.9.3
PLL Configurations
2.9.4
Special PLL Macros
2.9.5
User Flow
2.9.6
Sample Implementations
2.9.6.1
Frequency Synthesis
2.9.6.2
Adjustable Clock Delay
2.9.7
Clock Skew Minimization
2.10
Embedded Memory
2.11
Other Architectural Features
2.12
Programming
3
Package Pin Assignments
4
Revision History
Microchip FPGA Support
Microchip Information
2.9.6 Sample Implementations
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