31.8.3 Control C
| Name: | CTRLC |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HDRDLY[1:0] | BRKLEN[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GTIME[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 11:10 – HDRDLY[1:0] LIN Host Header Delay
This field is only valid when using the LIN header command (CTRLB.LINCMD = 0x2).
| Value | Description |
|---|---|
| 0x0 |
Delay between break and sync transmission is 1 bit time. Delay between sync and ID transmission is 1 bit time. |
| 0x1 |
Delay between break and sync transmission is 4 bit time. Delay between sync and ID transmission is 4 bit time. |
| 0x2 |
Delay between break and sync transmission is 8 bit time. Delay between sync and ID transmission is 4 bit time. |
| 0x3 |
Delay between break and sync transmission is 14 bit time. Delay between sync and ID transmission is 4 bit time. |
Bits 9:8 – BRKLEN[1:0] LIN Host Break Length
| Value | Description |
|---|---|
| 0x0 | Break field transmission is 13 bit times |
| 0x1 | Break field transmission is 17 bit times |
| 0x2 | Break field transmission is 21 bit times |
| 0x3 | Break field transmission is 26 bit times |
Bits 2:0 – GTIME[2:0] Guard Time
These bits define the guard time when using RS485 mode (CTRLA.FORM = 0x0 or CTRLA.FORM = 0x1, and CTRLA.TXPO = 0x3).
For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the transmit enable pin (TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted.