16.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	7:0								SWRST
0x01 ... 0x03	Reserved
0x04	SYNCBUSY	7:0	GENCTRL5	GENCTRL4	GENCTRL3	GENCTRL2	GENCTRL1	GENCTRL0		SWRST
		15:8						GENCTRL8	GENCTRL7	GENCTRL6
		23:16
		31:24
0x08 ... 0x1F	Reserved
0x20	GENCTRL0	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x24	GENCTRL1	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x28	GENCTRL2	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x2C	GENCTRL3	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x30	GENCTRL4	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x34	GENCTRL5	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x38	GENCTRL6	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x3C	GENCTRL7	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x40	GENCTRL8	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x44 ... 0x7F	Reserved
0x80	PCHCTRL0	7:0	WRTLOCK	CHEN			GEN[3:0]
		15:8
		23:16
		31:24
...
0x0134	PCHCTRL45	7:0	WRTLOCK	CHEN			GEN[3:0]
		15:8
		23:16
		31:24