21.8.9 32.768 kHz Internal Oscillator (OSC32K) Control
| Name: | OSC32K |
| Offset: | 0x18 |
| Reset: | 0x0000 0080 (Writing action by User required) |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CALIB[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WRTLOCK | STARTUP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ONDEMAND | RUNSTDBY | EN1K | EN32K | ENABLE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 0 | 0 |
Bits 22:16 – CALIB[6:0] Oscillator Calibration
These bits control the oscillator calibration. The calibration values must be loaded by the user from the NVM Software Calibration Area.
Bit 12 – WRTLOCK Write Lock
This bit locks the OSC32K register for future writes, effectively freezing the OSC32K configuration.
| Value | Description |
|---|---|
| 0 | The OSC32K configuration is not locked. |
| 1 | The OSC32K configuration is locked. |
Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time
These bits select start-up time for the oscillator.
The OSCULP32K oscillator is used as input clock to the start-up counter.
| STARTUP[2:0] | Number of OSC32K clock cycles | Approximate Equivalent Time [ms] |
|---|---|---|
| 0x0 | 3 | 0.092 |
| 0x1 | 4 | 0.122 |
| 0x2 | 6 | 0.183 |
| 0x3 | 10 | 0.305 |
| 0x4 | 18 | 0.549 |
| 0x5 | 34 | 1.038 |
| 0x6 | 66 | 2.014 |
| 0x7 | 130 | 3.967 |
Note:
- Start-up time is given by STARTUP + three OSC32K cycles.
- The given time assumes an XTAL frequency of 32.768 kHz.
Bit 7 – ONDEMAND On Demand Control
This bit controls how the OSC32K behaves when a peripheral clock request is detected. For details, refer to OSC32K Sleep Behavior.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the OSC32K behaves during standby sleep mode. For details, refer to OSC32K Sleep Behavior.
Bit 3 – EN1K 1.024 kHz Output Enable
| Value | Description |
|---|---|
| 0 | The 1.024 kHz output is disabled. |
| 1 | The 1.024 kHz output is enabled, and available internally only for RTC. |
Bit 2 – EN32K 32.768 kHz Output Enable
| Value | Description |
|---|---|
| 0 | The 32.768 kHz output is disabled. |
| 1 | The 32.768 kHz output is enabled, and can be routed to GCLK/GCLK_IO. |
Bit 1 – ENABLE Oscillator Enable
| Value | Description |
|---|---|
| 0 | The oscillator is disabled. |
| 1 | The oscillator is enabled. |