41.8.10 Synchronization Busy
| Name: | SYNCBUSY |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATABUF | DATA | ENABLE | SWRST | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – DATABUF Data Buffer
This bit is set when DATABUF register is written.
This bit is cleared when DATABUF synchronization is completed.
| Value | Description |
|---|---|
| 0 | No ongoing synchronized access. |
| 1 | Synchronized access is ongoing. |
Bit 2 – DATA Data
This bit is set when DATA register is written.
This bit is cleared when DATA synchronization is completed.
| Value | Description |
|---|---|
| 0 | No ongoing synchronized access. |
| 1 | Synchronized access is ongoing. |
Bit 1 – ENABLE DAC Enable Status
This bit is set when CTRLA.ENABLE bit is written.
This bit is cleared when CTRLA.ENABLE synchronization is completed.
| Value | Description |
|---|---|
| 0 | No ongoing synchronization. |
| 1 | Synchronization is ongoing. |
Bit 0 – SWRST Software Reset
This bit is set when CTRLA.SWRST bit is written.
This bit is cleared when CTRLA.SWRST synchronization is completed.
| Value | Description |
|---|---|
| 0 | No ongoing synchronization. |
| 1 | Synchronization is ongoing. |