41.8.2 Control B

Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected

Bit 76543210 
 REFSEL[1:0]DITHER VPDLEFTADJIOENEOEN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 7:6 – REFSEL[1:0] Reference Selection

This bit field selects the Reference Voltage for the DAC.

ValueNameDescription
0x0 INTREF Internal voltage reference, supplied by the bandgap (refer to SUPC.VREF.SEL for voltage level information)
0x1 VDDANA Analog voltage supply
0x2 VREFA External reference
0x3 Reserved

Bit 5 – DITHER Dithering Mode

This bit controls dithering operation according to 41.6.8.4 Dithering mode.

ValueDescription
0 Dithering mode is disabled.
1 Dithering mode is enabled.

Bit 3 – VPD Voltage Pump Disabled

This bit controls the behavior of the voltage pump.

ValueDescription
0 Voltage pump is turned on/off automatically
1 Voltage pump is disabled.

Bit 2 – LEFTADJ Left-Adjusted Data

This bit controls how the 10-bit conversion data is adjusted in the Data and Data Buffer registers.

ValueDescription
0 DATA and DATABUF registers are right-adjusted.
1 DATA and DATABUF registers are left-adjusted.

Bit 1 – IOEN Internal Output Enable

ValueDescription
0 Internal DAC output not enabled.
1 Internal DAC output enabled to be used by the AC or ADC.

Bit 0 – EOEN External Output Enable

ValueDescription
0 The DAC output is turned off.
1 The high-drive output buffer drives the DAC output to the VOUT pin.