16.8.2 Synchronization Busy

Name: SYNCBUSY
Offset: 0x04
Reset: 0x00000000
Property: 

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
      GENCTRL8GENCTRL7GENCTRL6 
Access RRR 
Reset 000 
Bit 76543210 
 GENCTRL5GENCTRL4GENCTRL3GENCTRL2GENCTRL1GENCTRL0 SWRST 
Access RRRRRRR 
Reset 0000000 

Bits 2, 3, 4, 5, 6, 7, 8, 9, 10 – GENCTRL Generator Control n Synchronization Busy

This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is complete, or when clock switching operation is complete.

This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is started.

Bit 0 – SWRST Software Reset Synchronization Busy

This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete.

This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started.