28.8.5 Data Output Value

This register sets the data output drive value for the individual I/O pins in the PORT.

This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers.

Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Name: OUT
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 OUT[31:24] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 2322212019181716 
 OUT[23:16] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 15141312111098 
 OUT[15:8] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 
Bit 76543210 
 OUT[7:0] 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 

Bits 31:0 – OUT[31:0] PORT Data Output Value

For pins configured as outputs via the Data Direction register (DIR), these bits set the logical output drive level.

For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN), these bits will set the input pull direction.

ValueDescription
0 The I/O pin output is driven low, or the input is connected to an internal pull-down.
1 The I/O pin output is driven high, or the input is connected to an internal pull-up.