24.12.10 Alarm Value in Clock/Calendar mode
(CTRLA.MODE=2)
The 32-bit value of
ALARM is continuously compared with the 32-bit CLOCK value, based on the masking set by
MASK.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG.ALARM) is set on the next counter cycle, and the counter is
cleared if CTRLA.MATCHCLR is '1'.Note: This register is write-synchronized:
SYNCBUSY.ALARM0 must be checked to ensure the ALARM register synchronization is
complete.
| Name: | ALARM |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection,
Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | YEAR[5:0] | MONTH[3:2] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | MONTH[1:0] | DAY[4:0] | HOUR[4] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | HOUR[3:0] | MINUTE[5:2] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | MINUTE[1:0] | SECOND[5:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:26 – YEAR[5:0] Year
The alarm year.
Years are only matched if MASK.SEL is 6
Bits 25:22 – MONTH[3:0] Month
The alarm month.
Months are matched only if MASK.SEL is greater than 4.
Bits 21:17 – DAY[4:0] Day
The alarm day. Days
are matched only if MASK.SEL is greater than 3.
Bits 16:12 – HOUR[4:0] Hour
The alarm hour.
Hours are matched only if MASK.SEL is greater than 2.
Bits 11:6 – MINUTE[5:0] Minute
The alarm minute.
Minutes are matched only if MASK.SEL is greater than 1.
Bits 5:0 – SECOND[5:0] Second
The alarm second.
Seconds are matched only if MASK.SEL is greater than 0.
