24.12.11 Alarm Mask in Clock/Calendar mode (CTRLA.MODE=2)

Note: This register is write-synchronized: SYNCBUSY.MASK0 must be checked to ensure the MASK register synchronization is complete.
Name: MASK
Offset: 0x24
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized

Bit 76543210 
      SEL[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 2:0 – SEL[2:0] Alarm Mask Selection

These bits define which bit groups of ALARM are valid.

ValueNameDescription
0x0 OFF Alarm Disabled
0x1 SS Match seconds only
0x2 MMSS Match seconds and minutes only
0x3 HHMMSS Match seconds, minutes, and hours only
0x4 DDHHMMSS Match seconds, minutes, hours, and days only
0x5 MMDDHHMMSS Match seconds, minutes, hours, days, and months only
0x6 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years
0x7 - Reserved